From 945b0d39e8e0ecc9587f9a148a3c24526ab6a4ec Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Wed, 2 Mar 2022 11:01:17 +0100
Subject: [PATCH] Ready for review.
---
.../lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
index 5282bbf542..5478ec55c5 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
@@ -50,7 +50,7 @@ ARCHITECTURE tb OF tb_ddrctrl_pack IS
CONSTANT c_out_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
FUNCTION c_testv_init RETURN STD_LOGIC_VECTOR IS
- VARIABLE temp : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
+ VARIABLE temp : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
BEGIN
FOR I IN 0 TO g_nof_streams-1 LOOP
temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
@@ -78,7 +78,7 @@ BEGIN
-- Start the testbench.
tb_end <= '0';
- WAIT UNTIL rising_edge(clk); -- align to rising edge
+ WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*2;
--
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