added components for ip_arria10_e3sge3

libraries/technology/pll/tech_pll_clk25.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
 LIBRARY ip_stratixiv_pll_clk25_lib;
+LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
 
 ENTITY tech_pll_clk25 IS
   GENERIC (

libraries/technology/pll/tech_pll_component_pkg.vhd

@@ -175,5 +175,60 @@ PACKAGE tech_pll_component_pkg IS
 --  );
 --  END COMPONENT;
 
+
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_arria10_e3sge3_pll_xgmii_mac_clocks IS
+  PORT (
+    pll_refclk0   : in  std_logic := '0'; --   pll_refclk0.clk
+    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_locked    : out std_logic;        --    pll_locked.pll_locked
+    outclk0       : out std_logic;        --       outclk0.clk
+    pll_cal_busy  : out std_logic;        --  pll_cal_busy.pll_cal_busy
+    outclk1       : out std_logic         --       outclk1.clk
+  );
+  END COMPONENT;
+
+  COMPONENT ip_arria10_e3sge3_pll_clk200 IS
+  PORT
+  (
+    rst       : IN STD_LOGIC  := '0';
+    refclk    : IN STD_LOGIC  := '0';
+    outclk_0  : OUT STD_LOGIC ;
+    outclk_1  : OUT STD_LOGIC ;
+    outclk_2  : OUT STD_LOGIC ;
+    locked    : OUT STD_LOGIC 
+  );
+  END COMPONENT;
+
+  COMPONENT ip_arria10_e3sge3_pll_clk25 IS
+  PORT
+  (
+    rst       : IN STD_LOGIC  := '0';
+    refclk    : IN STD_LOGIC  := '0';
+    outclk_0  : OUT STD_LOGIC ;
+    outclk_1  : OUT STD_LOGIC ;
+    outclk_2  : OUT STD_LOGIC ;
+    outclk_3  : OUT STD_LOGIC ;
+    locked    : OUT STD_LOGIC 
+  );
+  END COMPONENT;
+
+  COMPONENT ip_arria10_e3sge3_pll_clk125 IS
+  PORT
+  (
+    rst       : IN STD_LOGIC  := '0';
+    refclk    : IN STD_LOGIC  := '0';
+    outclk_0  : OUT STD_LOGIC ;
+    outclk_1  : OUT STD_LOGIC ;
+    outclk_2  : OUT STD_LOGIC ;
+    outclk_3  : OUT STD_LOGIC ;
+    locked    : OUT STD_LOGIC 
+  );
+  END COMPONENT;
+
+  
 END tech_pll_component_pkg;
 

libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd

@@ -42,6 +42,7 @@ USE common_lib.common_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
+LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
 
 ENTITY tech_pll_xgmii_mac_clocks IS
   GENERIC (

libraries/technology/technology_select_pkg.vhd

@@ -32,5 +32,6 @@ PACKAGE technology_select_pkg IS
 
   CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
   --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+  --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
   
 END technology_select_pkg;