From 9320e1ebe36b787aef24aeb546e3d9df3ade91a6 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 20 Jan 2016 16:05:50 +0000
Subject: [PATCH] added components for ip_arria10_e3sge3
---
libraries/technology/clkbuf/tech_clkbuf.vhd | 12 ++++
.../clkbuf/tech_clkbuf_component_pkg.vhd | 12 ++++
libraries/technology/fifo/hdllib.cfg | 2 +-
.../fifo/tech_fifo_component_pkg.vhd | 68 ++++++++++++++++++-
libraries/technology/fifo/tech_fifo_dc.vhd | 7 ++
.../fifo/tech_fifo_dc_mixed_widths.vhd | 7 ++
libraries/technology/fifo/tech_fifo_sc.vhd | 7 ++
.../flash/tech_flash_asmi_parallel.vhd | 6 ++
.../flash/tech_flash_component_pkg.vhd | 51 ++++++++++++++
.../flash/tech_flash_remote_update.vhd | 6 ++
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 1 +
.../tech_fpga_temp_sens_component_pkg.vhd | 9 +++
.../tech_fpga_voltage_sens.vhd | 1 +
.../tech_fpga_voltage_sens_component_pkg.vhd | 18 +++++
.../tech_fractional_pll_clk125.vhd | 1 +
.../tech_fractional_pll_clk200.vhd | 1 +
.../tech_fractional_pll_component_pkg.vhd | 31 +++++++++
.../iobuf/tech_iobuf_component_pkg.vhd | 32 +++++++++
.../technology/iobuf/tech_iobuf_ddio_in.vhd | 9 ++-
.../technology/iobuf/tech_iobuf_ddio_out.vhd | 9 ++-
.../clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ddio/compile_ip.tcl | 15 ++--
.../ip_arria10_e3sge3/ddio/generate_ip.sh | 4 +-
.../flash/asmi_parallel/compile_ip.tcl | 5 +-
.../flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 7 +-
.../flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk125/hdllib.cfg | 2 +-
.../pll_clk200/compile_ip.tcl | 5 +-
.../ip_arria10_e3sge3/pll_clk200/hdllib.cfg | 2 +-
.../pll_clk25/compile_ip.tcl | 3 +-
.../ip_arria10_e3sge3/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/temp_sense/hdllib.cfg | 2 +-
.../voltage_sense/hdllib.cfg | 2 +-
libraries/technology/pll/tech_pll_clk125.vhd | 1 +
libraries/technology/pll/tech_pll_clk200.vhd | 1 +
libraries/technology/pll/tech_pll_clk25.vhd | 1 +
.../technology/pll/tech_pll_component_pkg.vhd | 55 +++++++++++++++
.../pll/tech_pll_xgmii_mac_clocks.vhd | 1 +
.../technology/technology_select_pkg.vhd | 1 +
44 files changed, 378 insertions(+), 35 deletions(-)
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 764f5ebc8b..f7bb50c7ae 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
+LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
ENTITY tech_clkbuf IS
GENERIC (
@@ -55,4 +56,15 @@ BEGIN
);
END GENERATE;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 AND g_clock_net="GLOBAL" GENERATE
+ u0 : ip_arria10_e3sge3_clkbuf_global
+ PORT MAP (
+ inclk => inclk, -- inclk
+ outclk => outclk -- outclk
+ );
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
index f1f267913a..efc4c049e0 100644
--- a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
@@ -36,6 +36,18 @@ PACKAGE tech_clkbuf_component_pkg IS
outclk : out std_logic -- altclkctrl_output.outclk
);
END COMPONENT;
+
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e3sge3_clkbuf_global IS
+ PORT (
+ inclk : in std_logic := '0'; -- altclkctrl_input.inclk
+ outclk : out std_logic -- altclkctrl_output.outclk
+ );
+ END COMPONENT;
END tech_clkbuf_component_pkg;
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index ed4bcec4fd..358adc9cda 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 0cc6e4e078..69b2209adb 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -93,7 +93,7 @@ PACKAGE tech_fifo_component_pkg IS
-----------------------------------------------------------------------------
- -- ip_stratixiv
+ -- ip_arria10
-----------------------------------------------------------------------------
COMPONENT ip_arria10_fifo_sc IS
@@ -156,5 +156,71 @@ PACKAGE tech_fifo_component_pkg IS
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
END COMPONENT;
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e3sge3_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_fifo_dc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_fifo_component_pkg;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index bbee822068..f19df9a1b4 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
+LIBRARY ip_arria10_e3sge3_fifo_lib;
ENTITY tech_fifo_dc IS
GENERIC (
@@ -67,5 +68,11 @@ BEGIN
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_fifo_dc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 9912a6a20a..b0b982ff7e 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
+LIBRARY ip_arria10_e3sge3_fifo_lib;
ENTITY tech_fifo_dc_mixed_widths IS
GENERIC (
@@ -67,5 +68,11 @@ BEGIN
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_fifo_dc_mixed_widths
+ GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 7481ddeed2..ee60048e85 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
+LIBRARY ip_arria10_e3sge3_fifo_lib;
ENTITY tech_fifo_sc IS
GENERIC (
@@ -65,5 +66,11 @@ BEGIN
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_fifo_sc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index e1d9c339af..2de89479dd 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -30,6 +30,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
+LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
@@ -76,5 +77,10 @@ BEGIN
u0 : ip_arria10_asmi_parallel
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_asmi_parallel
+ PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 243954ce2a..63d64c81fe 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -112,6 +112,51 @@ PACKAGE tech_flash_component_pkg IS
);
end component ip_arria10_remote_update;
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ component ip_arria10_e3sge3_asmi_parallel is
+ port (
+ addr : in std_logic_vector(31 downto 0);
+ clkin : in std_logic;
+ datain : in std_logic_vector(7 downto 0);
+ rden : in std_logic;
+ read : in std_logic;
+ sector_erase : in std_logic;
+ shift_bytes : in std_logic;
+ wren : in std_logic;
+ write : in std_logic;
+ busy : out std_logic;
+ data_valid : out std_logic;
+ dataout : out std_logic_vector(7 downto 0);
+ illegal_erase : out std_logic;
+ illegal_write : out std_logic;
+ reset : in std_logic;
+ sce : in std_logic_vector(2 downto 0);
+ en4b_addr : in std_logic
+ );
+ end component ip_arria10_e3sge3_asmi_parallel;
+
+ -- note the EPCQ-L1024 device appears not to be supported yet.
+ -- the EPCA-512 was chosen instead
+
+ component ip_arria10_e3sge3_remote_update is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ param : in std_logic_vector(2 downto 0);
+ read_param : in std_logic;
+ reconfig : in std_logic;
+ reset : in std_logic;
+ reset_timer : in std_logic;
+ write_param : in std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(31 downto 0)
+ );
+ end component ip_arria10_e3sge3_remote_update;
+
function tech_flash_addr_w( technology: in integer ) return integer;
function tech_flash_data_w( technology: in integer ) return integer;
@@ -127,6 +172,9 @@ package body tech_flash_component_pkg is
if technology = c_tech_arria10 then
return 32;
end if;
+ if technology = c_tech_arria10_e3sge3 then
+ return 32;
+ end if;
end;
function tech_flash_data_w( technology : in integer ) return integer is
@@ -137,6 +185,9 @@ package body tech_flash_component_pkg is
if technology = c_tech_arria10 then
return 32;
end if;
+ if technology = c_tech_arria10_e3sge3 then
+ return 32;
+ end if;
end;
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 44eb52db91..17c360efb8 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -30,6 +30,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
+LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
ENTITY tech_flash_remote_update IS
GENERIC (
@@ -66,4 +67,9 @@ BEGIN
u0 : ip_arria10_remote_update
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_remote_update
+ PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index e785842196..1b69fc737e 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
+LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index a0080a1af5..8c9c255c0f 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -35,5 +35,14 @@ PACKAGE tech_fpga_temp_sens_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e3sge3_temp_sense IS
+ PORT (
+ corectl : IN STD_LOGIC := '0'; -- corectl.corectl
+ eoc : OUT STD_LOGIC; -- eoc.eoc
+ reset : IN STD_LOGIC := '0'; -- reset.reset
+ tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) -- tempout.tempout
+ );
+ END COMPONENT;
+
END tech_fpga_temp_sens_component_pkg;
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index 56f8d9ded7..f9111d1c90 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
+LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 87a657044a..9780d0870b 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -44,5 +44,23 @@ PACKAGE tech_fpga_voltage_sens_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e3sge3_voltage_sense IS
+ PORT (
+ clock_clk : in STD_LOGIC := '0';
+ reset_sink_reset : in STD_LOGIC;
+ controller_csr_address : in STD_LOGIC := '0';
+ controller_csr_read : in STD_LOGIC := '0';
+ controller_csr_write : in STD_LOGIC := '0';
+ controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_address : in STD_LOGIC_VECTOR(3 downto 0) := "0000";
+ sample_store_csr_read : in STD_LOGIC := '0';
+ sample_store_csr_write : in STD_LOGIC := '0';
+ sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_irq_irq : out STD_LOGIC
+ );
+ END COMPONENT;
+
END tech_fpga_voltage_sens_component_pkg;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 4c2814fa2b..00836d4503 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
+LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 6dd4ec5834..191326b8c9 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
+LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
index c8e1bcd975..8b0db6b937 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
@@ -56,6 +56,37 @@ PACKAGE tech_fractional_pll_component_pkg IS
pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
);
END COMPONENT;
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e3sge3_fractional_pll_clk200 IS
+ PORT
+ (
+ outclk0 : out std_logic; -- outclk0.clk
+ outclk1 : out std_logic; -- outclk1.clk
+ outclk2 : out std_logic; -- outclk2.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_fractional_pll_clk125 IS
+ PORT
+ (
+ outclk0 : out std_logic; -- outclk0.clk
+ outclk1 : out std_logic; -- outclk1.clk
+ outclk2 : out std_logic; -- outclk2.clk
+ outclk3 : out std_logic; -- outclk2.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ );
+ END COMPONENT;
END tech_fractional_pll_component_pkg;
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index dce04fc43e..2d66aebd7d 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -93,4 +93,36 @@ PACKAGE tech_iobuf_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e3sge3_ddio_in IS
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_ddio_out IS
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_iobuf_component_pkg;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 252f592c2e..97531852b5 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ddio_lib;
LIBRARY ip_arria10_ddio_lib;
+LIBRARY ip_arria10_e3sge3_ddio_lib;
ENTITY tech_iobuf_ddio_in IS
GENERIC (
@@ -60,5 +61,11 @@ BEGIN
GENERIC MAP (g_width)
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_ddio_in
+ GENERIC MAP (g_width)
+ PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+ END GENERATE;
-END ARCHITECTURE;
\ No newline at end of file
+END ARCHITECTURE;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index efbf517b73..b8f7773440 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ddio_lib;
LIBRARY ip_arria10_ddio_lib;
+LIBRARY ip_arria10_e3sge3_ddio_lib;
ENTITY tech_iobuf_ddio_out IS
GENERIC (
@@ -60,5 +61,11 @@ BEGIN
GENERIC MAP (g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_ddio_out
+ GENERIC MAP (g_width)
+ PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+ END GENERATE;
-END ARCHITECTURE;
\ No newline at end of file
+END ARCHITECTURE;
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 526066edf3..2c7493ddd9 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_clkbuf_global
-hdl_library_clause_name = ip_arria10_e3sge3_clkbuf_global_altclkctrl_150
+hdl_library_clause_name = ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index 39198d5513..a211be7af7 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,8 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
+ set IP_DIR_IN "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated_in/"
+ set IP_DIR_OUT "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated_out/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
@@ -40,14 +41,14 @@ if {$IPMODEL=="PHY"} {
#vmap ip_arria10_e3sge3_ddio_in_1 ./work/
#vmap ip_arria10_e3sge3_ddio_out_1 ./work/
- vlog -sv "$IP_DIR/../altera_gpio_core_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151
- vlog -sv "$IP_DIR/../altera_gpio_core_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_core_151
+ vlog -sv "$IP_DIR_IN/../altera_gpio_core20_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151
+ vlog -sv "$IP_DIR_OUT/../altera_gpio_core20_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_core_151
- vcom "$IP_DIR/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_v2653ny.vhd" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_151
- vcom "$IP_DIR/ip_arria10_e3sge3_ddio_in_1.vhd"
+ vcom "$IP_DIR_IN/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq.vhd" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_151
+ vcom "$IP_DIR_IN/ip_arria10_e3sge3_ddio_in_1.vhd"
- vcom "$IP_DIR/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_out_1_altera_gpio_151_26jftvi.vhd" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_151
- vcom "$IP_DIR/ip_arria10_e3sge3_ddio_out_1.vhd"
+ vcom "$IP_DIR_OUT/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_out_1_altera_gpio_151_pqwimxi.vhd" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_151
+ vcom "$IP_DIR_OUT/ip_arria10_e3sge3_ddio_out_1.vhd"
} else {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
index 03a3952849..361db703aa 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
@@ -39,5 +39,5 @@
#qsys-generate --help
# Only generate the source IP
-qsys-generate ip_arria10_e3sge3_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
-qsys-generate ip_arria10_e3sge3_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e3sge3_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated_in
+qsys-generate ip_arria10_e3sge3_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated_out
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index 2877158aba..7cc37bb4c7 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -30,5 +30,6 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/flash/asmi_p
vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
- vlog "$IP_DIR/../altera_asmi_parallel_151/sim/ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151_bvuboea.v" -work ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
- vcom "$IP_DIR/ip_arria10_e3sge3_asmi_parallel.vhd"
+vlog "$IP_DIR/../altera_asmi_parallel_151/sim/ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151_jy7dk3i.v" -work ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
+vcom "$IP_DIR/ip_arria10_e3sge3_asmi_parallel.vhd"
+
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 1846f81fa0..52a2a86a6b 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_asmi_parallel
-hdl_library_clause_name = ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_150
+hdl_library_clause_name = ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 4df969080c..6da4cd63b6 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -31,6 +31,7 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/flash/remote
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151 ./work/
- vlog "$IP_DIR/../altera_remote_update_core_151/sim/altera_remote_update_core.v" -work ip_arria10_e3sge3_remote_update_altera_remote_update_core_151
- vlog "$IP_DIR/../altera_remote_update_151/sim/ip_arria10_e3sge3_remote_update_altera_remote_update_151_eltl22a.v" -work ip_arria10_e3sge3_remote_update_altera_remote_update_151
- vcom "$IP_DIR/ip_arria10_e3sge3_remote_update.vhd"
+vlog "$IP_DIR/../altera_remote_update_core_151/sim/altera_remote_update_core.v" -work ip_arria10_e3sge3_remote_update_altera_remote_update_core_151
+vlog "$IP_DIR/../altera_remote_update_151/sim/ip_arria10_e3sge3_remote_update_altera_remote_update_151_fdzfjma.v" -work ip_arria10_e3sge3_remote_update_altera_remote_update_151
+vcom "$IP_DIR/ip_arria10_e3sge3_remote_update.vhd"
+
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index 367db94cb0..0f8147f4fb 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_remote_update
-hdl_library_clause_name = ip_arria10_e3sge3_remote_update_altera_remote_update_150
+hdl_library_clause_name = ip_arria10_e3sge3_remote_update_altera_remote_update_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 18e3203e53..7caa46b972 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_fractional_pll_clk125
-hdl_library_clause_name = ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_150
+hdl_library_clause_name = ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index 0d965639f7..8050fce67e 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_fractional_pll_clk200
-hdl_library_clause_name = ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_150
+hdl_library_clause_name = ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index d1e944fae5..e1a730824c 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -32,7 +32,7 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk125/g
vmap ip_arria10_e3sge3_pll_clk125_altera_iopll_151 ./work/
- vlog "$IP_DIR/../altera_iopll_151/sim/ip_arria10_pll_e3sge3_clk125_altera_iopll_151_hxjbkfi.vo" -work ip_arria10_e3sge3_pll_clk125_altera_iopll_151
+ vlog "$IP_DIR/../altera_iopll_151/sim/ip_arria10_e3sge3_pll_clk125_altera_iopll_151_lzlggeq.vo" -work ip_arria10_e3sge3_pll_clk125_altera_iopll_151
vcom "$IP_DIR/ip_arria10_e3sge3_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index 6ac8ad3f06..6857212230 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_pll_clk125
-hdl_library_clause_name = ip_arria10_e3sge3_pll_clk125_altera_iopll_150
+hdl_library_clause_name = ip_arria10_e3sge3_pll_clk125_altera_iopll_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 13995db55b..10b86dcf0f 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -32,7 +32,6 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk200/g
vmap ip_arria10_e3sge3_pll_clk200_altera_iopll_151 ./work/
- vlog "$IP_DIR/../altera_iopll_151/sim/ip_arria10_e3sge3_pll_clk200_altera_iopll_151_etouxvq.vo" -work ip_arria10_e3sge3_pll_clk200_altera_iopll_151
- vcom "$IP_DIR/ip_arria10_e3sge3_pll_clk200.vhd"
-
+vlog "$IP_DIR/../altera_iopll_151/sim/ip_arria10_e3sge3_pll_clk200_altera_iopll_151_2qckecy.vo" -work ip_arria10_e3sge3_pll_clk200_altera_iopll_151
+vcom "$IP_DIR/ip_arria10_e3sge3_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index 3de8a4d5f6..26ec0a211e 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_pll_clk200
-hdl_library_clause_name = ip_arria10_e3sge3_pll_clk200_altera_iopll_150
+hdl_library_clause_name = ip_arria10_e3sge3_pll_clk200_altera_iopll_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index d5925d5928..7c21e1477b 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -32,7 +32,6 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/pll_clk25/ge
vmap ip_arria10_e3sge3_pll_clk25_altera_iopll_151 ./work/
- vlog "$IP_DIR/../altera_iopll_151/sim/ip_arria10_e3sge3_pll_clk25_altera_iopll_151_o3lgeqy.vo" -work ip_arria10_e3sge3_pll_clk25_altera_iopll_151
+ vlog "$IP_DIR/../altera_iopll_151/sim/ip_arria10_e3sge3_pll_clk25_altera_iopll_151_roshl5q.vo" -work ip_arria10_e3sge3_pll_clk25_altera_iopll_151
vcom "$IP_DIR/ip_arria10_e3sge3_pll_clk25.vhd"
-
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index 3acd3db179..37d30f2de3 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_pll_clk25
-hdl_library_clause_name = ip_arria10_e3sge3_pll_clk25_altera_iopll_150
+hdl_library_clause_name = ip_arria10_e3sge3_pll_clk25_altera_iopll_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index 8694c86e56..a0be0646dd 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_pll_xgmii_mac_clocks
-hdl_library_clause_name = ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150
+hdl_library_clause_name = ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 6d75f4fabb..63d27bbaeb 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_temp_sense
-hdl_library_clause_name = ip_arria10_e3sge3_temp_sense_altera_temp_sense_150
+hdl_library_clause_name = ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index d8e8fe792b..6f541b5a46 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_voltage_sense
-hdl_library_clause_name = ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_150
+hdl_library_clause_name = ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index d322fb5973..0c13ffc207 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
+LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
ENTITY tech_pll_clk125 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 1ad91b9f48..539bf15f15 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
+LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
ENTITY tech_pll_clk200 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 40e666e4a5..13301ec202 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
+LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
ENTITY tech_pll_clk25 IS
GENERIC (
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index 7b7abf0467..fab118242b 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -174,6 +174,61 @@ PACKAGE tech_pll_component_pkg IS
-- locked : OUT STD_LOGIC
-- );
-- END COMPONENT;
+
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e3sge3_pll_xgmii_mac_clocks IS
+ PORT (
+ pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ outclk0 : out std_logic; -- outclk0.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ outclk1 : out std_logic -- outclk1.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_pll_clk200 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_pll_clk25 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_pll_clk125 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
END tech_pll_component_pkg;
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index a3748668a1..7bc38df5ee 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -42,6 +42,7 @@ USE common_lib.common_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
+LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
diff --git a/libraries/technology/technology_select_pkg.vhd b/libraries/technology/technology_select_pkg.vhd
index d523ac4fb9..055faa9b0a 100644
--- a/libraries/technology/technology_select_pkg.vhd
+++ b/libraries/technology/technology_select_pkg.vhd
@@ -32,5 +32,6 @@ PACKAGE technology_select_pkg IS
CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
--CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+ --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
END technology_select_pkg;
--
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