Changed unb1_reorder DDR3 selection to single rank master

applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd

@@ -67,7 +67,7 @@ ARCHITECTURE tb OF tb_unb1_reorder IS
   CONSTANT c_sa_clk_period   : TIME := 6.4 ns; 
   CONSTANT c_pps_period      : NATURAL := 1000; 
 
-  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
 
   -- DUT
   SIGNAL clk                 : STD_LOGIC := '0';