From 929c9307a490e882142c7b56184b45f0f8b8d675 Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Wed, 29 Apr 2015 07:50:15 +0000
Subject: [PATCH] Changed unb1_reorder DDR3 selection to single rank master

---
 applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd b/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd
index 13cfca2ae8..a789dde4ff 100644
--- a/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd
+++ b/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd
@@ -67,7 +67,7 @@ ARCHITECTURE tb OF tb_unb1_reorder IS
   CONSTANT c_sa_clk_period   : TIME := 6.4 ns; 
   CONSTANT c_pps_period      : NATURAL := 1000; 
 
-  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
 
   -- DUT
   SIGNAL clk                 : STD_LOGIC := '0';
-- 
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