-Added generics to tb_mms_st_histogram and updated comment block.

libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd

@@ -23,18 +23,14 @@
 -- Author: 
 -- . Daniel van der Schuur
 -- Purpose:
--- . TB to verify correct MM access across clock domain by eye.
+-- . 
 -- ModelSim usage:
 -- . (open project, compile)
 -- . (load simulation config)
 -- . as 8
 -- . run -a
 -- Description:
--- . reg_mosi/miso uses traditional _reg instance to cross clock domain and 
---   therefor does not need additional checks.
--- . ram_mosi/miso uses several common_reg_cross_domain instances to let the
---   MM buses cross MM<->DP clock domain in both directions. Should work, but
---   is not a proven method - hence this TB.
+-- . 
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib, mm_lib, dp_lib;
@@ -48,6 +44,12 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE dp_lib.tb_dp_pkg.ALL;
 
 ENTITY tb_mms_st_histogram IS
+  GENERIC(
+    g_nof_instances     : NATURAL := 1;
+    g_data_w            : NATURAL := 8;
+    g_nof_bins          : NATURAL := 256;
+    g_nof_data_per_sync : NATURAL := 1024
+  );
 END tb_mms_st_histogram;
 
 
@@ -96,10 +98,10 @@ BEGIN
   ----------------------------------------------------------------------------
   u_mms_st_histogram : ENTITY work.mms_st_histogram
   GENERIC MAP(
-    g_nof_instances     => 1,
-    g_data_w            => 8,
-    g_nof_bins          => 256,
-    g_nof_data_per_sync => 1024
+    g_nof_instances     => g_nof_instances,
+    g_data_w            => g_data_w,
+    g_nof_bins          => g_nof_bins,
+    g_nof_data_per_sync => g_nof_data_per_sync
   )
   PORT MAP (
     dp_clk       => dp_clk,