-Fixed mosi bus switching based on ram_fill_inst;

-Verified correct tb_mms_st_histogram.vhd by eye.

libraries/dsp/st/src/vhdl/mms_st_histogram.vhd

@@ -90,21 +90,23 @@ ARCHITECTURE str OF mms_st_histogram IS
   SIGNAL common_ram_cr_cw_rd_mosi : t_mem_mosi;
   SIGNAL common_ram_cr_cw_rd_miso : t_mem_miso; 
 
-  SIGNAL reg_mosi_arr  : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
-  SIGNAL reg_miso_arr  : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0);
+--  SIGNAL reg_mosi_arr  : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
+--  SIGNAL reg_miso_arr  : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0);
 
   SIGNAL ram_mosi_arr  : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
   SIGNAL ram_miso_arr  : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0);
 
-  SIGNAL ram_clear        : STD_LOGIC;
-  SIGNAL ram_clearing_arr : STD_LOGIC_VECTOR(g_nof_instances-1 DOWNTO 0);
+  SIGNAL ram_clear         : STD_LOGIC;
+  SIGNAL ram_clearing_arr  : STD_LOGIC_VECTOR(g_nof_instances-1 DOWNTO 0);
 
-  SIGNAL ram_fill_inst    : STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
-  SIGNAL ram_fill         : STD_LOGIC;
-  SIGNAL ram_filling      : STD_LOGIC;
-  SIGNAL nxt_ram_filling  : STD_LOGIC;
-  SIGNAL address          : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
-  SIGNAL nxt_address      : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
+  SIGNAL ram_fill_inst     : STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
+  SIGNAL ram_fill_inst_int : NATURAL;
+
+  SIGNAL ram_fill          : STD_LOGIC;
+  SIGNAL ram_filling       : STD_LOGIC;
+  SIGNAL nxt_ram_filling   : STD_LOGIC;
+  SIGNAL address           : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
+  SIGNAL nxt_address       : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
    
 BEGIN 
 
@@ -155,20 +157,20 @@ BEGIN
   );
 
 
-  -------------------------------------------------------------------------------
-  -- MM multiplexer from g_nof_instances to 1
-  -------------------------------------------------------------------------------
-  u_common_mem_mux_reg : ENTITY common_lib.common_mem_mux
-  GENERIC MAP (    
-    g_nof_mosi    => g_nof_instances,
-    g_mult_addr_w => c_reg_adr_w
-  )
-  PORT MAP (
-    mosi     => reg_mosi,
-    miso     => reg_miso,
-    mosi_arr => reg_mosi_arr,
-    miso_arr => reg_miso_arr
-  );
+--  -------------------------------------------------------------------------------
+--  -- MM multiplexer from g_nof_instances to 1
+--  -------------------------------------------------------------------------------
+--  u_common_mem_mux_reg : ENTITY common_lib.common_mem_mux
+--  GENERIC MAP (    
+--    g_nof_mosi    => g_nof_instances,
+--    g_mult_addr_w => c_reg_adr_w
+--  )
+--  PORT MAP (
+--    mosi     => reg_mosi,
+--    miso     => reg_miso,
+--    mosi_arr => reg_mosi_arr,
+--    miso_arr => reg_miso_arr
+--  );
 
 
   -------------------------------------------------------------------------------
@@ -209,19 +211,38 @@ BEGIN
   nxt_ram_filling <= '0' WHEN TO_UINT(address)=c_addr_high ELSE '1' WHEN ram_fill='1' ELSE ram_filling;
   nxt_address <= (OTHERS=>'0') WHEN ram_filling='0' ELSE INCR_UVEC(address, 1) WHEN ram_filling='1' ELSE address;
 
+  -- Help signal for bus selection
+  ram_fill_inst_int <= TO_UINT(ram_fill_inst);
+
   -- Do read request on ram_mosi when ram_filling
-  ram_mosi_arr(TO_UINT(ram_fill_inst)).rd                              <= ram_filling;
-  ram_mosi_arr(TO_UINT(ram_fill_inst)).address(c_ram_adr_w-1 DOWNTO 0) <= address;
+  p_mosi_arr: PROCESS (ram_filling, address, ram_fill_inst_int)
+  BEGIN
+    FOR i IN 0 TO g_nof_instances-1 LOOP
+      ram_mosi_arr(i) <= c_mem_mosi_rst;
+      IF i = ram_fill_inst_int THEN
+        ram_mosi_arr(i).rd                              <= ram_filling;
+        ram_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0) <= address;
+      END IF;
+    END LOOP;
+  END PROCESS;
 
   -- Forward the read histogram data from ram_miso into write mosi of dual clock RAM
-  nxt_common_ram_cr_cw_wr_mosi.wr                              <= ram_miso_arr(TO_UINT(ram_fill_inst)).rdval;
-  nxt_common_ram_cr_cw_wr_mosi.wrdata(c_ram_dat_w-1 DOWNTO 0)  <= ram_miso_arr(TO_UINT(ram_fill_inst)).rddata(c_ram_dat_w-1 DOWNTO 0);
-  nxt_common_ram_cr_cw_wr_mosi.address(c_ram_adr_w-1 DOWNTO 0) <= address;
+  p_rd_miso_to_wr_mosi : PROCESS(ram_miso_arr, ram_fill_inst_int, address)
+  BEGIN
+    nxt_common_ram_cr_cw_wr_mosi <= common_ram_cr_cw_wr_mosi;
+    FOR i IN 0 TO g_nof_instances-1 LOOP
+      IF i = ram_fill_inst_int THEN
+        nxt_common_ram_cr_cw_wr_mosi.wr                              <= ram_miso_arr(i).rdval;
+        nxt_common_ram_cr_cw_wr_mosi.wrdata(c_ram_dat_w-1 DOWNTO 0)  <= ram_miso_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0);
+        nxt_common_ram_cr_cw_wr_mosi.address(c_ram_adr_w-1 DOWNTO 0) <= address;
+      END IF;
+    END LOOP;
+  END PROCESS;
 
   -- Registers
   p_clk : PROCESS(dp_clk, dp_rst) IS
   BEGIN
-    IF dp_rst = '0' THEN
+    IF dp_rst = '1' THEN
       common_ram_cr_cw_wr_mosi <= c_mem_mosi_rst;
       address <= (OTHERS=>'0');
       ram_filling <= '0';

libraries/dsp/st/src/vhdl/st_histogram_reg.vhd

@@ -64,7 +64,7 @@ END st_histogram_reg;
 
 ARCHITECTURE rtl OF st_histogram_reg IS
 
-  CONSTANT nof_addresses : NATURAL := 2;
+  CONSTANT nof_addresses : NATURAL := 3;
 
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
                                   adr_w    => ceil_log2(nof_addresses),
@@ -97,6 +97,7 @@ BEGIN
       -- Access event, register values
       mm_ram_clear <= '0';
       mm_ram_fill <= '0';
+      mm_ram_fill_inst <= (OTHERS=>'0');
  
     ELSIF rising_edge(mm_clk) THEN
       -- Read access defaults

libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd

@@ -123,14 +123,19 @@ BEGIN
   -- Perform MM read 
   p_verify_mm_read : PROCESS
   BEGIN
-    st_histogram_ram_mosi <= c_mem_mosi_rst;
+    st_histogram_reg_mosi <= c_mem_mosi_rst;
     proc_common_wait_until_low(mm_clk, mm_rst);
     proc_common_wait_some_cycles(mm_clk, 10);
 
-    -- Read address 7 of the RAM
-    proc_mem_mm_bus_rd(7, mm_clk, st_histogram_ram_mosi); 
+    -- Start RAM filling
+    proc_mem_mm_bus_wr(2, 1, mm_clk, st_histogram_reg_mosi); 
 
     proc_common_wait_some_cycles(mm_clk, 10);
+
+    -- Read filling status
+    proc_mem_mm_bus_rd(2, mm_clk, st_histogram_reg_mosi); 
+
+    proc_common_wait_some_cycles(mm_clk, 1000);
     tb_end <= '1';
     WAIT;
   END PROCESS;