From 920bbdab65ff0e63ce7fb2c50d838b017a073fe3 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 28 May 2021 14:36:02 +0200
Subject: [PATCH] -Added generics to tb_mms_st_histogram and updated comment
block.
---
.../dsp/st/tb/vhdl/tb_mms_st_histogram.vhd | 22 ++++++++++---------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
index ac2cbaa8d2..85c43527be 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
@@ -23,18 +23,14 @@
-- Author:
-- . Daniel van der Schuur
-- Purpose:
--- . TB to verify correct MM access across clock domain by eye.
+-- .
-- ModelSim usage:
-- . (open project, compile)
-- . (load simulation config)
-- . as 8
-- . run -a
-- Description:
--- . reg_mosi/miso uses traditional _reg instance to cross clock domain and
--- therefor does not need additional checks.
--- . ram_mosi/miso uses several common_reg_cross_domain instances to let the
--- MM buses cross MM<->DP clock domain in both directions. Should work, but
--- is not a proven method - hence this TB.
+-- .
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, mm_lib, dp_lib;
@@ -48,6 +44,12 @@ USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
ENTITY tb_mms_st_histogram IS
+ GENERIC(
+ g_nof_instances : NATURAL := 1;
+ g_data_w : NATURAL := 8;
+ g_nof_bins : NATURAL := 256;
+ g_nof_data_per_sync : NATURAL := 1024
+ );
END tb_mms_st_histogram;
@@ -96,10 +98,10 @@ BEGIN
----------------------------------------------------------------------------
u_mms_st_histogram : ENTITY work.mms_st_histogram
GENERIC MAP(
- g_nof_instances => 1,
- g_data_w => 8,
- g_nof_bins => 256,
- g_nof_data_per_sync => 1024
+ g_nof_instances => g_nof_instances,
+ g_data_w => g_data_w,
+ g_nof_bins => g_nof_bins,
+ g_nof_data_per_sync => g_nof_data_per_sync
)
PORT MAP (
dp_clk => dp_clk,
--
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