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Commit 8ed4abf0 authored by Eric Kooistra's avatar Eric Kooistra
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Apply dp_ready FIFO flow control in generate loop, instead of using...

Apply dp_ready FIFO flow control in generate loop, instead of using func_dp_stream_arr_set(dplink_siso_arr, dp_ready, 'READY')
parent ae9605f1
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1 merge request!381rx_clk -> dp_clk FIFO in JESD204b component.
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