Skip to content
Snippets Groups Projects
Commit 8ed4abf0 authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Apply dp_ready FIFO flow control in generate loop, instead of using...

Apply dp_ready FIFO flow control in generate loop, instead of using func_dp_stream_arr_set(dplink_siso_arr, dp_ready, 'READY')
parent ae9605f1
No related branches found
No related tags found
1 merge request!381rx_clk -> dp_clk FIFO in JESD204b component.
Pipeline #72097 passed
Status
Pipeline
Created by
Stages
Actions
Passed

00:13:20

avatar
Download artifacts

No artifacts found