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RTSD
HDL
Commits
8b75d180
Commit
8b75d180
authored
3 years ago
by
Eric Kooistra
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Added p_verify_snk_in_data.
parent
7a1f47f4
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1 merge request
!190
Resolve L2SDP-210
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libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+15
-1
15 additions, 1 deletion
libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
with
15 additions
and
1 deletion
libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+
15
−
1
View file @
8b75d180
...
...
@@ -24,7 +24,7 @@
-- Description:
-- u_tx u_rx
-- ___________________ ___________________
-- |dp_offload_tx_v3| |dp_offload_rx |
-- |dp_offload_tx_v3
| |dp_offload_rx |
-- stimuli_src -->| |--->| |--> verify_snk
-- | in out | | | in out |
-- |___________________| | |___________________|
...
...
@@ -251,6 +251,7 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
SIGNAL
verify_snk_out
:
t_dp_siso
:
=
c_dp_siso_rdy
;
SIGNAL
verify_snk_in
:
t_dp_sosi
;
SIGNAL
verify_snk_in_data
:
STD_LOGIC_VECTOR
(
g_data_w
-1
DOWNTO
0
);
SIGNAL
prev_verify_snk_in_data
:
STD_LOGIC_VECTOR
(
g_data_w
-1
DOWNTO
0
);
BEGIN
...
...
@@ -557,6 +558,19 @@ BEGIN
WAIT
;
END
PROCESS
;
p_verify_snk_in_data
:
PROCESS
BEGIN
WAIT
UNTIL
rising_edge
(
dp_clk
);
prev_verify_snk_in_data
<=
verify_snk_in
.
data
(
g_data_w
-1
DOWNTO
0
);
IF
verify_snk_in
.
sop
=
'1'
THEN
ASSERT
TO_UINT
(
verify_snk_in
.
data
)
MOD
g_pkt_len
=
0
REPORT
"Wrong decoded data at sop."
SEVERITY
ERROR
;
ELSIF
verify_snk_in
.
eop
=
'1'
THEN
ASSERT
TO_UINT
(
verify_snk_in
.
data
)
MOD
g_pkt_len
=
g_pkt_len
-
1
REPORT
"Wrong decoded data at eop."
SEVERITY
ERROR
;
ELSIF
verify_snk_in
.
valid
=
'1'
THEN
ASSERT
TO_UINT
(
verify_snk_in
.
data
)
=
TO_UINT
(
prev_verify_snk_in_data
)
+
1
REPORT
"Wrong decoded data at valid."
SEVERITY
ERROR
;
END
IF
;
END
PROCESS
;
------------------------------------------------------------------------------
-- Auxiliary
...
...
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