diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index 200c61a94cf251ebe6021954755f7926634298c2..3e48cfc8ff3b39a3adc5a267db94ba4fc2076583 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -24,7 +24,7 @@
 -- Description:
 --                 u_tx                     u_rx
 --                 ___________________      ___________________ 
---                |dp_offload_tx_v3|    |dp_offload_rx      |
+--                |dp_offload_tx_v3   |    |dp_offload_rx      |
 -- stimuli_src -->|                   |--->|                   |--> verify_snk
 --                | in            out | |  | in            out |
 --                |___________________| |  |___________________|
@@ -251,6 +251,7 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
   SIGNAL verify_snk_out             : t_dp_siso := c_dp_siso_rdy;
   SIGNAL verify_snk_in              : t_dp_sosi;
   SIGNAL verify_snk_in_data         : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+  SIGNAL prev_verify_snk_in_data    : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
 
 BEGIN
 
@@ -557,6 +558,19 @@ BEGIN
     WAIT;
   END PROCESS;
 
+  p_verify_snk_in_data : PROCESS
+  BEGIN
+    WAIT UNTIL rising_edge(dp_clk);
+    prev_verify_snk_in_data <= verify_snk_in.data(g_data_w-1 DOWNTO 0);
+    IF verify_snk_in.sop = '1' THEN
+      ASSERT TO_UINT(verify_snk_in.data) MOD g_pkt_len = 0 REPORT "Wrong decoded data at sop." SEVERITY ERROR;
+    ELSIF verify_snk_in.eop = '1' THEN
+      ASSERT TO_UINT(verify_snk_in.data) MOD g_pkt_len = g_pkt_len - 1 REPORT "Wrong decoded data at eop." SEVERITY ERROR;
+    ELSIF verify_snk_in.valid = '1' THEN
+      ASSERT TO_UINT(verify_snk_in.data) = TO_UINT(prev_verify_snk_in_data) + 1 REPORT "Wrong decoded data at valid." SEVERITY ERROR;
+    END IF;
+  END PROCESS;
+
 
   ------------------------------------------------------------------------------
   -- Auxiliary