Verify dp_sync = 0 in p_rd_rx_hdr_words.

libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd

@@ -86,7 +86,7 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
   CONSTANT c_sync_period              : NATURAL := 5;
   CONSTANT c_sync_offset              : NATURAL := 2;
   CONSTANT c_bsn_init                 : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := TO_DP_BSN(0);
-  CONSTANT c_nof_sync                 : NATURAL := 5;
+  CONSTANT c_nof_sync                 : NATURAL := 3;
   CONSTANT c_nof_packets              : NATURAL := c_sync_period * c_nof_sync;
 
   CONSTANT c_hdr_len                  : NATURAL := 7;
@@ -157,9 +157,9 @@ ARCHITECTURE tb OF tb_dp_offload_tx_v3 IS
 
   -- RX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
   CONSTANT c_expected_rx_hdr_word_arr : t_slv_32_arr(0 TO c_udp_offload_nof_hdr_words-1) := ( -- word address
-                                                                             X"0000000B",     -- 0   = dp_bsn[31:0]        -- dynamic value obtained from simulation
+                                                                             X"00000002",     -- 0   = dp_bsn[31:0]        -- dynamic value obtained from simulation
                                                                              X"00000000",     -- 1   = dp_bsn[63:32]
-                                                                             X"00000000",     -- 2   = dp_sync             -- dynamic value obtained from simulation
+                                                                             X"00000001",     -- 2   = dp_sync             -- dynamic value obtained from simulation
                                                                              X"03040506",     -- 3   = dp_reserved[31:0]
                                                                              X"00000102",     -- 4   = dp_reserved[47:32]
                                                                              X"00000000",     -- 5   = udp_checksum
@@ -520,8 +520,7 @@ BEGIN
     VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   BEGIN
     proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sync);
-    proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sync);
-    proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sync);
+    -- Check first packet after sync with dp_sync = 1
     -- wait some latency until header fields of this sync packet are available via MM
     proc_common_wait_some_cycles(dp_clk, 10);
     print_str("");
@@ -534,9 +533,27 @@ BEGIN
       -- View word in wave window
       rx_hdr_word <= v_word;
       -- Verify expected word
-      ASSERT c_expected_rx_hdr_word_arr(I) = v_word REPORT "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr(I)) SEVERITY ERROR;
+      ASSERT v_word = c_expected_rx_hdr_word_arr(I) REPORT "Unexpected rx_hdr_word at address " & int_to_str(I) & ", expected " & slv_to_hex(c_expected_rx_hdr_word_arr(I)) SEVERITY ERROR;
     END LOOP;
     print_str("");
+
+    -- Check dp_bsn and dp_sync of second packet after sync with dp_sync = 0
+    proc_common_wait_until_hi_lo(dp_clk, verify_snk_in.sop);
+    -- wait some latency until header fields of this sync packet are available via MM
+    proc_common_wait_some_cycles(dp_clk, 10);
+    -- dp_bsn lo
+    proc_mem_mm_bus_rd(0, mm_clk, reg_dp_offload_rx_hdr_dat_mosi);
+    proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+    v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 DOWNTO 0);
+    rx_hdr_word <= v_word;  -- View word in wave window
+    ASSERT v_word = INCR_UVEC(c_expected_rx_hdr_word_arr(0), 1) REPORT "Unexpected dp_bsn from MM" SEVERITY ERROR;
+    -- dp_sync
+    proc_mem_mm_bus_rd(2, mm_clk, reg_dp_offload_rx_hdr_dat_mosi);
+    proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
+    v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 DOWNTO 0);
+    rx_hdr_word <= v_word;  -- View word in wave window
+    ASSERT v_word = TO_UVEC(0, 32) REPORT "Unexpected dp_sync from MM" SEVERITY ERROR;
+
     WAIT;
   END PROCESS;