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Commit 8ab8ea76 authored by Job van Wee's avatar Job van Wee
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functionally ready

parent a20fe8b6
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1 merge request!215Resolve L2SDP-660
...@@ -6,11 +6,11 @@ hdl_lib_technology = ...@@ -6,11 +6,11 @@ hdl_lib_technology =
synth_files = synth_files =
src/vhdl/ddrctrl_address_counter.vhd src/vhdl/ddrctrl_address_counter.vhd
src/vhdl/pack.vhd src/vhdl/ddrctrl_pack.vhd
test_bench_files = test_bench_files =
tb/vhdl/tb_ddrctrl_address_counter.vhd tb/vhdl/tb_ddrctrl_address_counter.vhd
tb/vhdl/tb_pack.vhd tb/vhdl/tb_ddrctrl_pack.vhd
regression_test_vhdl = regression_test_vhdl =
......
...@@ -34,7 +34,7 @@ LIBRARY IEEE, dp_lib; ...@@ -34,7 +34,7 @@ LIBRARY IEEE, dp_lib;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
ENTITY pack IS ENTITY ddrctrl_pack IS
GENERIC ( GENERIC (
g_nof_streams : POSITIVE := 12; g_nof_streams : POSITIVE := 12;
...@@ -48,9 +48,9 @@ ENTITY pack IS ...@@ -48,9 +48,9 @@ ENTITY pack IS
out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
); );
END pack; END ddrctrl_pack;
ARCHITECTURE rtl OF pack IS ARCHITECTURE rtl OF ddrctrl_pack IS
BEGIN BEGIN
......
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author: Job van Wee -- Author: Job van Wee
-- Purpose: Self checking and self-stopping tb for pack.vhd -- Purpose: Self checking and self-stopping tb for ddrctrl_pack.vhd
-- Usage: -- Usage:
-- > run -a -- > run -a
...@@ -32,7 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL; ...@@ -32,7 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
ENTITY tb_pack IS ENTITY tb_ddrctrl_pack IS
GENERIC ( GENERIC (
g_nof_streams : POSITIVE := 12; g_nof_streams : POSITIVE := 12;
...@@ -40,16 +40,24 @@ ENTITY tb_pack IS ...@@ -40,16 +40,24 @@ ENTITY tb_pack IS
g_sim_model : BOOLEAN := TRUE g_sim_model : BOOLEAN := TRUE
); );
END tb_pack; END tb_ddrctrl_pack;
ARCHITECTURE tb OF tb_pack IS ARCHITECTURE tb OF tb_ddrctrl_pack IS
CONSTANT c_clk_freq : NATURAL := 200; -- MHz CONSTANT c_clk_freq : NATURAL := 200; -- MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
CONSTANT c_data_w : NATURAL := g_nof_streams * g_data_w; -- 168 CONSTANT c_data_w : NATURAL := g_nof_streams * g_data_w; -- 168
CONSTANT c_testv : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := "111111111111111111111111110011111111110000111111110000001111110000000011110000000000110000000000000000000000000000000000000011000000000011110000000011111100000011111111"; FUNCTION c_testv_init RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
BEGIN
FOR I IN 0 TO g_nof_streams-1 LOOP
temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
END LOOP;
RETURN temp;
END FUNCTION c_testv_init;
CONSTANT c_testv : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := c_testv_init;
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_end : STD_LOGIC := '0';
...@@ -63,10 +71,6 @@ BEGIN ...@@ -63,10 +71,6 @@ BEGIN
clk <= NOT clk OR tb_end AFTER c_clk_period/2; clk <= NOT clk OR tb_end AFTER c_clk_period/2;
check_data : FOR I IN 0 TO g_nof_streams - 1 GENERATE
ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) REPORT "Data does not match" SEVERITY ERROR;
END GENERATE;
p_mm : PROCESS p_mm : PROCESS
BEGIN BEGIN
...@@ -76,7 +80,7 @@ BEGIN ...@@ -76,7 +80,7 @@ BEGIN
WAIT FOR c_clk_period*2; WAIT FOR c_clk_period*2;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I); in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
END LOOP; END LOOP;
...@@ -95,7 +99,17 @@ BEGIN ...@@ -95,7 +99,17 @@ BEGIN
WAIT; WAIT;
END PROCESS; END PROCESS;
u_pack : ENTITY work.pack p_verify : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF rising_edge(clk) THEN
check_data : FOR I IN 0 TO g_nof_streams - 1 LOOP
ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) REPORT "Data does not match, I = " & NATURAL'image(I) SEVERITY ERROR;
END LOOP;
END IF;
END PROCESS;
u_pack : ENTITY work.ddrctrl_pack
GENERIC MAP ( GENERIC MAP (
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
g_data_w => g_data_w g_data_w => g_data_w
......
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