diff --git a/applications/lofar2/libraries/ddrctrl/hdllib.cfg b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
index 1f31cda7082550a92970d81752672dc90f5a3128..0e403b02febd38781f129a332a9128e7f1b455b1 100644
--- a/applications/lofar2/libraries/ddrctrl/hdllib.cfg
+++ b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
@@ -6,11 +6,11 @@ hdl_lib_technology =
synth_files =
src/vhdl/ddrctrl_address_counter.vhd
- src/vhdl/pack.vhd
+ src/vhdl/ddrctrl_pack.vhd
test_bench_files =
tb/vhdl/tb_ddrctrl_address_counter.vhd
- tb/vhdl/tb_pack.vhd
+ tb/vhdl/tb_ddrctrl_pack.vhd
regression_test_vhdl =
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
similarity index 92%
rename from applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd
rename to applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
index a986050bbc914f2323ba8f3565d83bab91675e9a..af4debebfbf77ccd11549c9d9fef80edc9c68fd2 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
@@ -34,7 +34,7 @@ LIBRARY IEEE, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY pack IS
+ENTITY ddrctrl_pack IS
GENERIC (
g_nof_streams : POSITIVE := 12;
@@ -48,9 +48,9 @@ ENTITY pack IS
out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
);
-END pack;
+END ddrctrl_pack;
-ARCHITECTURE rtl OF pack IS
+ARCHITECTURE rtl OF ddrctrl_pack IS
BEGIN
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
similarity index 59%
rename from applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd
rename to applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
index 2dc8d1b65dec93400cf528922d98713e8b96d7ae..fa86f4db9a598f114b6355726f69bb6cd1e4d1d2 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for pack.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_pack.vhd
-- Usage:
-- > run -a
@@ -32,29 +32,37 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_pack IS
+ENTITY tb_ddrctrl_pack IS
GENERIC (
-
- g_nof_streams : POSITIVE := 12;
- g_data_w : NATURAL := 14;
- g_sim_model : BOOLEAN := TRUE
+
+ g_nof_streams : POSITIVE := 12;
+ g_data_w : NATURAL := 14;
+ g_sim_model : BOOLEAN := TRUE
);
-END tb_pack;
+END tb_ddrctrl_pack;
+
+ARCHITECTURE tb OF tb_ddrctrl_pack IS
-ARCHITECTURE tb OF tb_pack IS
+ CONSTANT c_clk_freq : NATURAL := 200; -- MHz
+ CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
- CONSTANT c_clk_freq : NATURAL := 200; -- MHz
- CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
+ CONSTANT c_data_w : NATURAL := g_nof_streams * g_data_w; -- 168
- CONSTANT c_data_w : NATURAL := g_nof_streams * g_data_w; -- 168
+ FUNCTION c_testv_init RETURN STD_LOGIC_VECTOR IS
+ VARIABLE temp : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+ BEGIN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
+ END LOOP;
+ RETURN temp;
+ END FUNCTION c_testv_init;
+ CONSTANT c_testv : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := c_testv_init;
- CONSTANT c_testv : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := "111111111111111111111111110011111111110000111111110000001111110000000011110000000000110000000000000000000000000000000000000011000000000011110000000011111100000011111111";
-
- SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL clk : STD_LOGIC := '1';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init);
SIGNAL out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
@@ -63,10 +71,6 @@ BEGIN
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
- check_data : FOR I IN 0 TO g_nof_streams - 1 GENERATE
- ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) REPORT "Data does not match" SEVERITY ERROR;
- END GENERATE;
-
p_mm : PROCESS
BEGIN
@@ -76,7 +80,7 @@ BEGIN
WAIT FOR c_clk_period*2;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
+ in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
END LOOP;
@@ -85,7 +89,7 @@ BEGIN
in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0) <= in_sosi_arr(g_nof_streams-1).data(g_data_w - 1 DOWNTO 0);
gen_switch_data : FOR I IN 1 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= in_sosi_arr(I-1).data(g_data_w - 1 DOWNTO 0);
- END LOOP;
+ END LOOP;
END LOOP;
WAIT FOR c_clk_period*4;
@@ -95,7 +99,17 @@ BEGIN
WAIT;
END PROCESS;
- u_pack : ENTITY work.pack
+ p_verify : PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ IF rising_edge(clk) THEN
+ check_data : FOR I IN 0 TO g_nof_streams - 1 LOOP
+ ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) REPORT "Data does not match, I = " & NATURAL'image(I) SEVERITY ERROR;
+ END LOOP;
+ END IF;
+ END PROCESS;
+
+ u_pack : ENTITY work.ddrctrl_pack
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_data_w => g_data_w