commit for revieuw

applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd

-LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
 USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY address_counter IS
   GENERIC (
@@ -13,11 +15,8 @@ ENTITY address_counter IS
   PORT (
     clk	     		      : IN  STD_LOGIC;
     rst               : IN  STD_LOGIC;
-    in_data  		      : IN  STD_LOGIC_VECTOR(func_tech_ddr_ctlr_data_w( g_tech_ddr )-1 DOWNTO 0);
-    in_data_enable	  : IN  STD_LOGIC;
-    out_data 		      : OUT STD_LOGIC_VECTOR(func_tech_ddr_ctlr_data_w( g_tech_ddr )-1 DOWNTO 0);
-    out_data_enable	  : OUT STD_LOGIC;
-    adr			          : OUT NATURAL range 0 to 2**(sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )))-1
+    in_sosi           : IN  t_dp_sosi;
+    out_mosi          : OUT t_mem_ctlr_mosi
   );
 END address_counter;
 
@@ -26,20 +25,20 @@ ARCHITECTURE rtl OF address_counter IS
   CONSTANT c_data_w	: NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
   CONSTANT c_adr_w	: NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); --27;
 
-  SIGNAL   s_adr    : NATURAL range 0 to 2**(c_adr_w)-1;
+  SIGNAL   s_adr    : NATURAL range 0 to 2**(c_adr_w)-1 := 0;
 
 BEGIN
 
-  out_data(c_data_w - 1 DOWNTO 0) <= in_data(c_data_w - 1 DOWNTO 0);
-  out_data_enable <= in_data_enable;
-  adr <= s_adr;
+  out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
+  out_mosi.wr                            <= in_sosi.valid;
+  out_mosi.address(c_adr_w -1 DOWNTO 0)  <= TO_UVEC(s_adr, c_adr_w);
 
   p_clk : PROCESS(clk)
   BEGIN
     IF rising_edge(clk) THEN
       IF rst = '1' THEN
         s_adr <= 0;                                                            -- https://stackoverflow.com/questions/9989913/vhdl-how-to-use-clk-and-reset-in-process
-      ELSIF in_data_enable = '1' THEN
+      ELSIF in_sosi.valid = '1' THEN
         IF (s_adr = 2**(c_adr_w) - 1) THEN
           s_adr <= 0;
         ELSE

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd

@@ -20,12 +20,15 @@
 --
 --------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE IEEE.MATH_REAL.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
 
 ENTITY tb_address_counter IS
   GENERIC (
@@ -51,13 +54,23 @@ ARCHITECTURE tb OF tb_address_counter IS
 
   SIGNAL    in_data           : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
   SIGNAL    in_data_enable    : STD_LOGIC;
+  SIGNAL    in_sosi           : t_dp_sosi       := c_dp_sosi_init;
 
   SIGNAL    out_data          : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
   SIGNAL    out_data_enable   : STD_LOGIC;
-  SIGNAL    adr               : NATURAL range 0 to 2**(c_adr_w)-1;
+  SIGNAL    adr               : NATURAL RANGE 0 TO 2**(c_adr_w)-1 := 0;
+  SIGNAL    out_mosi          : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
 
 BEGIN
 
+  in_sosi.data(c_data_w - 1 DOWNTO 0)    <= in_data(c_data_w - 1 DOWNTO 0);
+  in_sosi.valid                          <= in_data_enable;
+
+  out_data(c_data_w - 1 DOWNTO 0)        <= out_mosi.wrdata(c_data_w - 1 DOWNTO 0);
+  out_data_enable                        <= out_mosi.wr;
+  adr                                    <= TO_UINT(out_mosi.address);
+
+
   clk               <= NOT clk OR tb_end AFTER c_clk_period/2;
 
   p_mm : PROCESS
@@ -152,12 +165,10 @@ BEGIN
   PORT MAP (
     clk               => clk,
     rst               => rst,
-    in_data           => in_data,
-    in_data_enable    => in_data_enable,
+    in_sosi           => in_sosi,
+
+    out_mosi          => out_mosi
 
-    out_data          => out_data,
-    out_data_enable   => out_data_enable,
-    adr               => adr
   );
 
 END tb;