diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd
index e82a0b25c6a28cfbdf58df1ab8e9f03a2dadae1a..617497902e442566ec7cbb1b07abd5d77062fe39 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd
@@ -1,9 +1,11 @@
-LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
ENTITY address_counter IS
GENERIC (
@@ -13,11 +15,8 @@ ENTITY address_counter IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
- in_data : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_data_w( g_tech_ddr )-1 DOWNTO 0);
- in_data_enable : IN STD_LOGIC;
- out_data : OUT STD_LOGIC_VECTOR(func_tech_ddr_ctlr_data_w( g_tech_ddr )-1 DOWNTO 0);
- out_data_enable : OUT STD_LOGIC;
- adr : OUT NATURAL range 0 to 2**(sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )))-1
+ in_sosi : IN t_dp_sosi;
+ out_mosi : OUT t_mem_ctlr_mosi
);
END address_counter;
@@ -26,20 +25,20 @@ ARCHITECTURE rtl OF address_counter IS
CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
CONSTANT c_adr_w : NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); --27;
- SIGNAL s_adr : NATURAL range 0 to 2**(c_adr_w)-1;
+ SIGNAL s_adr : NATURAL range 0 to 2**(c_adr_w)-1 := 0;
BEGIN
- out_data(c_data_w - 1 DOWNTO 0) <= in_data(c_data_w - 1 DOWNTO 0);
- out_data_enable <= in_data_enable;
- adr <= s_adr;
+ out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
+ out_mosi.wr <= in_sosi.valid;
+ out_mosi.address(c_adr_w -1 DOWNTO 0) <= TO_UVEC(s_adr, c_adr_w);
p_clk : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF rst = '1' THEN
s_adr <= 0; -- https://stackoverflow.com/questions/9989913/vhdl-how-to-use-clk-and-reset-in-process
- ELSIF in_data_enable = '1' THEN
+ ELSIF in_sosi.valid = '1' THEN
IF (s_adr = 2**(c_adr_w) - 1) THEN
s_adr <= 0;
ELSE
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd
index a5582ae65187f94a3af6ecd75914b0da6a281c10..f83b8d7793aafd9ab4f128cd2e3d0492128ec5c3 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd
@@ -20,44 +20,57 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
ENTITY tb_address_counter IS
GENERIC (
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
- g_sim_model : BOOLEAN := TRUE
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+ g_sim_model : BOOLEAN := TRUE
);
END tb_address_counter;
ARCHITECTURE tb OF tb_address_counter IS
- CONSTANT c_clk_freq : NATURAL := 200; -- MHz
- CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
+ CONSTANT c_clk_freq : NATURAL := 200; -- MHz
+ CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
- CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- 576
- CONSTANT c_adr_w : NATURAL := 4;
+ CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- 576
+ CONSTANT c_adr_w : NATURAL := 4;
- SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC;
SIGNAL in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
SIGNAL in_data_enable : STD_LOGIC;
+ SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
SIGNAL out_data_enable : STD_LOGIC;
- SIGNAL adr : NATURAL range 0 to 2**(c_adr_w)-1;
+ SIGNAL adr : NATURAL RANGE 0 TO 2**(c_adr_w)-1 := 0;
+ SIGNAL out_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
BEGIN
+ in_sosi.data(c_data_w - 1 DOWNTO 0) <= in_data(c_data_w - 1 DOWNTO 0);
+ in_sosi.valid <= in_data_enable;
+
+ out_data(c_data_w - 1 DOWNTO 0) <= out_mosi.wrdata(c_data_w - 1 DOWNTO 0);
+ out_data_enable <= out_mosi.wr;
+ adr <= TO_UINT(out_mosi.address);
+
+
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
p_mm : PROCESS
@@ -152,12 +165,10 @@ BEGIN
PORT MAP (
clk => clk,
rst => rst,
- in_data => in_data,
- in_data_enable => in_data_enable,
+ in_sosi => in_sosi,
+
+ out_mosi => out_mosi
- out_data => out_data,
- out_data_enable => out_data_enable,
- adr => adr
);
END tb;