for mm_clk default using fpll

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -433,6 +433,7 @@ BEGIN
   gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
     u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
     GENERIC MAP (
+      g_use_fpll   => TRUE,
       g_technology => g_technology
     )
     PORT MAP (