From 807c73677aa9c8225f3f83df90b1134c8dbb1c0d Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 10 Sep 2015 09:51:36 +0000
Subject: [PATCH] for mm_clk default using fpll
---
.../uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd | 1 +
1 file changed, 1 insertion(+)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 8fdd4cf12a..eb24467a6b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -433,6 +433,7 @@ BEGIN
gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
GENERIC MAP (
+ g_use_fpll => TRUE,
g_technology => g_technology
)
PORT MAP (
--
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