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Commit 807c7367 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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for mm_clk default using fpll

parent 5cb0246b
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...@@ -433,6 +433,7 @@ BEGIN ...@@ -433,6 +433,7 @@ BEGIN
gen_mm_clk_hardware: IF g_sim = FALSE GENERATE gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
GENERIC MAP ( GENERIC MAP (
g_use_fpll => TRUE,
g_technology => g_technology g_technology => g_technology
) )
PORT MAP ( PORT MAP (
......
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