From 800591ef1f4ceaf5a8b1ce4241caa9e9a14a66cf Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 2 Apr 2015 14:24:43 +0000
Subject: [PATCH] Added default values to mm_Rst and mm_clk
---
libraries/io/ddr3/src/vhdl/ddr3.vhd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index dc78a1d67a..3545f3ee7e 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -48,8 +48,8 @@ ENTITY ddr3 IS
);
PORT (
-- MM clock + reset
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC := '0';
+ mm_clk : IN STD_LOGIC := '0';
ctlr_ref_clk : IN STD_LOGIC;
ctlr_rst : IN STD_LOGIC; -- asynchronous reset input to controller
--
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