diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index dc78a1d67a1e36cdef6fad23f28deeb1dad16768..3545f3ee7eccee34fb245906371de4a98d21c57e 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -48,8 +48,8 @@ ENTITY ddr3 IS
   );                      
   PORT (   
     -- MM clock + reset                                                             
-    mm_rst             : IN    STD_LOGIC;                                           
-    mm_clk             : IN    STD_LOGIC;                                                          
+    mm_rst             : IN    STD_LOGIC := '0';                                           
+    mm_clk             : IN    STD_LOGIC := '0';                                                          
     
     ctlr_ref_clk       : IN    STD_LOGIC;
     ctlr_rst           : IN    STD_LOGIC; -- asynchronous reset input to controller