From 7f482f03d40626fd429689b58df0b4d5fc64e6dc Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 12 May 2016 11:36:15 +0000
Subject: [PATCH] Added regression_test_vhdl, but without tb.

---
 libraries/technology/clkbuf/hdllib.cfg            | 3 +++
 libraries/technology/ddr/hdllib.cfg               | 3 +++
 libraries/technology/fifo/hdllib.cfg              | 3 +++
 libraries/technology/flash/hdllib.cfg             | 3 +++
 libraries/technology/fpga_temp_sens/hdllib.cfg    | 3 +++
 libraries/technology/fpga_voltage_sens/hdllib.cfg | 3 +++
 libraries/technology/fractional_pll/hdllib.cfg    | 3 +++
 libraries/technology/hdllib.cfg                   | 3 +++
 libraries/technology/iobuf/hdllib.cfg             | 3 +++
 libraries/technology/memory/hdllib.cfg            | 3 +++
 libraries/technology/mult/hdllib.cfg              | 3 +++
 libraries/technology/pll/hdllib.cfg               | 3 +++
 12 files changed, 36 insertions(+)

diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index a474f956a9..b442fb41b7 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -11,6 +11,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 227c51e85f..c574756270 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -30,6 +30,9 @@ test_bench_files =
     tech_ddr_mem_model_component_pkg.vhd
     tech_ddr_mem_model.vhd
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index cd2f4e75a3..3171d4a814 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -12,6 +12,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 3d9f76f1bc..32a88c6b82 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -16,6 +16,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index cbb8929e5c..defce62065 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 08112f7364..0cdb78df86 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 45a623dcb0..25a6c9dddf 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -13,6 +13,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index b63e66f46f..d60fcc4522 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index 53d656dc9d..e5881d26e0 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -11,6 +11,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index e1cdd1cdc4..9a30fa1d22 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -14,6 +14,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 73bc46a0cc..5d02f6cbc8 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -19,6 +19,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index aacb820117..32cbf9cd2e 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -18,6 +18,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
-- 
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