diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index a474f956a9dee0e1c8c2531afc255e920024d0fd..b442fb41b745e97c9e6d908a5ae618efe44a069b 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -11,6 +11,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 227c51e85f1fbd4d5e849628a7e5873c5a802969..c574756270c600fa5e9975436271a3fd37a6ba34 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -30,6 +30,9 @@ test_bench_files =
     tech_ddr_mem_model_component_pkg.vhd
     tech_ddr_mem_model.vhd
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index cd2f4e75a38d18a87eacc1984842991506a351b4..3171d4a81486a0dcf036d797eb9d09a353d5a6fe 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -12,6 +12,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 3d9f76f1bc3f9453d57e6ea64a4b9bb4eb1d7abc..32a88c6b82cdfb7381cea91b0db10d0766b40c8b 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -16,6 +16,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index cbb8929e5c291c36c7b18974303ca59a16255f28..defce62065952a7e305679da6b8f5105bbceffb9 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 08112f7364deee4ad91b5dcb54482b0ca36e1fae..0cdb78df86ea046c6d6e55850319eb6cbed72458 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 45a623dcb0b9d9f4f7e6d351b1ec995f845d920e..25a6c9dddf7e865fdb0c4420fee3c4a21e42502b 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -13,6 +13,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index b63e66f46f390914f6e2808640c76a737d92a7c5..d60fcc45224b2e92cc48715a7fbea58f6fd5db9a 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index 53d656dc9d56ae42ae6b22c7d976ad221f860631..e5881d26e0a8c2cb3e6947931f094094a5d3344c 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -11,6 +11,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index e1cdd1cdc425186d006d3af3a99f8a939cbbf7d1..9a30fa1d22cf80415bd347e98345b77db2deab0d 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -14,6 +14,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 73bc46a0cc54582998215df2db95ccec5a2f9fa4..5d02f6cbc8168caf745433bbac59796eedc0cfee 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -19,6 +19,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index aacb820117578592488eb7a5e24e25efb654c663..32cbf9cd2e74039ad3996fb53dbab87351ad4720 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -18,6 +18,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]