added dp_pipeline_ready to ease timing closure

applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd

@@ -92,6 +92,8 @@ ARCHITECTURE str OF sdp_beamformer_output IS
   SIGNAL dp_offload_tx_src_in      : t_dp_siso;
   SIGNAL ip_checksum_src_out       : t_dp_sosi;
   SIGNAL ip_checksum_src_in        : t_dp_siso;
+  SIGNAL dp_pipeline_ready_src_out : t_dp_sosi;
+  SIGNAL dp_pipeline_ready_src_in  : t_dp_siso;
 
   SIGNAL common_fifo_rd_req : STD_LOGIC;
   SIGNAL payload_err        : STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -269,6 +271,20 @@ BEGIN
     src_in  => ip_checksum_src_in
   );
 
+  -------------------------------------------------------------------------------
+  -- dp_pipeline_ready to ease timing closure
+  -------------------------------------------------------------------------------
+  u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+  PORT MAP(
+    rst => dp_rst,
+    clk => dp_clk,
+
+    snk_out => ip_checksum_src_in,
+    snk_in  => ip_checksum_src_out,
+    src_in  => dp_pipeline_ready_src_in,
+    src_out => dp_pipeline_ready_src_out
+  );
+
   -------------------------------------------------------------------------------
   -- mms_dp_xonoff
   ------------------------------------------------------------------------------- 
@@ -289,8 +305,8 @@ BEGIN
     dp_clk      => dp_clk, 
 
     -- ST sinks
-    snk_out_arr(0) => ip_checksum_src_in,  
-    snk_in_arr(0)  => ip_checksum_src_out, 
+    snk_out_arr(0) => dp_pipeline_ready_src_in,  
+    snk_in_arr(0)  => dp_pipeline_ready_src_out, 
     -- ST source
     src_in_arr(0)  => src_in, 
     src_out_arr(0) => out_sosi