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RTSD
HDL
Commits
7e557b92
Commit
7e557b92
authored
2 years ago
by
Reinier van der Walle
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added dp_pipeline_ready to ease timing closure
parent
cc211bd2
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1 merge request
!271
Resolve L2SDP-798
Pipeline
#34389
passed
2 years ago
Stage: simulation
Stage: synthesis
Changes
1
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1
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applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+27
-11
27 additions, 11 deletions
...s/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
with
27 additions
and
11 deletions
applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+
27
−
11
View file @
7e557b92
...
...
@@ -83,15 +83,17 @@ ARCHITECTURE str OF sdp_beamformer_output IS
CONSTANT
c_fifo_fill
:
NATURAL
:
=
c_sdp_cep_payload_nof_longwords
;
CONSTANT
c_fifo_size
:
NATURAL
:
=
c_fifo_fill
*
2
;
-- Make fifo size large enough for adding header and muxing beamsets.
SIGNAL
snk_in_concat
:
t_dp_sosi
;
SIGNAL
dp_packet_merge_src_out
:
t_dp_sosi
;
SIGNAL
dp_repack_data_src_out
:
t_dp_sosi
;
SIGNAL
dp_fifo_sc_src_out
:
t_dp_sosi
;
SIGNAL
dp_fifo_sc_src_in
:
t_dp_siso
;
SIGNAL
dp_offload_tx_src_out
:
t_dp_sosi
;
SIGNAL
dp_offload_tx_src_in
:
t_dp_siso
;
SIGNAL
ip_checksum_src_out
:
t_dp_sosi
;
SIGNAL
ip_checksum_src_in
:
t_dp_siso
;
SIGNAL
snk_in_concat
:
t_dp_sosi
;
SIGNAL
dp_packet_merge_src_out
:
t_dp_sosi
;
SIGNAL
dp_repack_data_src_out
:
t_dp_sosi
;
SIGNAL
dp_fifo_sc_src_out
:
t_dp_sosi
;
SIGNAL
dp_fifo_sc_src_in
:
t_dp_siso
;
SIGNAL
dp_offload_tx_src_out
:
t_dp_sosi
;
SIGNAL
dp_offload_tx_src_in
:
t_dp_siso
;
SIGNAL
ip_checksum_src_out
:
t_dp_sosi
;
SIGNAL
ip_checksum_src_in
:
t_dp_siso
;
SIGNAL
dp_pipeline_ready_src_out
:
t_dp_sosi
;
SIGNAL
dp_pipeline_ready_src_in
:
t_dp_siso
;
SIGNAL
common_fifo_rd_req
:
STD_LOGIC
;
SIGNAL
payload_err
:
STD_LOGIC_VECTOR
(
0
DOWNTO
0
);
...
...
@@ -269,6 +271,20 @@ BEGIN
src_in
=>
ip_checksum_src_in
);
-------------------------------------------------------------------------------
-- dp_pipeline_ready to ease timing closure
-------------------------------------------------------------------------------
u_dp_pipeline_ready
:
ENTITY
dp_lib
.
dp_pipeline_ready
PORT
MAP
(
rst
=>
dp_rst
,
clk
=>
dp_clk
,
snk_out
=>
ip_checksum_src_in
,
snk_in
=>
ip_checksum_src_out
,
src_in
=>
dp_pipeline_ready_src_in
,
src_out
=>
dp_pipeline_ready_src_out
);
-------------------------------------------------------------------------------
-- mms_dp_xonoff
-------------------------------------------------------------------------------
...
...
@@ -289,8 +305,8 @@ BEGIN
dp_clk
=>
dp_clk
,
-- ST sinks
snk_out_arr
(
0
)
=>
ip_checksum
_src_in
,
snk_in_arr
(
0
)
=>
ip_checksum
_src_out
,
snk_out_arr
(
0
)
=>
dp_pipeline_ready
_src_in
,
snk_in_arr
(
0
)
=>
dp_pipeline_ready
_src_out
,
-- ST source
src_in_arr
(
0
)
=>
src_in
,
src_out_arr
(
0
)
=>
out_sosi
...
...
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