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Commit 7d055f4b authored by Reinier van der Walle's avatar Reinier van der Walle
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added qsfp_leds_v2 and connected the DDR cal OK signal. 

Created the new unb2c_test_ddr_16G_I revision.
parent 69667ee7
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1 merge request!392added qsfp_leds_v2 and connected the DDR cal OK signal.
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boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G_I/hdllib.cfg 0 → 100644
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View file @ 7d055f4b
hdl_lib_name = unb2c_test_ddr_16G_I
hdl_library_clause_name = unb2c_test_ddr_16G_I_lib
hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
hdl_lib_include_ip =
# Comment all IP that is not used in this design
# DDR memory
ip_arria10_e2sg_ddr4_16g_1600_64b
synth_files =
unb2c_test_ddr_16G_I.vhd
test_bench_files =
tb_unb2c_test_ddr_16G_I.vhd
regression_test_vhdl =
tb_unb2c_test_ddr_16G_I.vhd
[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
$HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl # 4GB DDR4 model
$HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl # Unb2c 8GB DDR4 driver
$HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl # Unb2c 16GB-64b DDR4 driver
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus .
../../quartus .
../../src/hex hex
quartus_qsf_files =
$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_ddr_16G_I.sdc
$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_ddr_16G_I_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr_16G_I/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
$HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G_I/quartus/unb2c_test_ddr_16G_I_pins.tcl 0 → 100644
+ 297
− 0
View file @ 7d055f4b
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
# module I:
set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
set_location_assignment PIN_AR20 -to MB_I_OU.a[1]
set_location_assignment PIN_AP19 -to MB_I_OU.a[2]
set_location_assignment PIN_AR19 -to MB_I_OU.a[3]
set_location_assignment PIN_AR18 -to MB_I_OU.a[4]
set_location_assignment PIN_AT17 -to MB_I_OU.a[5]
set_location_assignment PIN_AU19 -to MB_I_OU.a[6]
set_location_assignment PIN_AT18 -to MB_I_OU.a[7]
set_location_assignment PIN_AL17 -to MB_I_OU.a[8]
set_location_assignment PIN_AM18 -to MB_I_OU.a[9]
set_location_assignment PIN_AM19 -to MB_I_OU.a[10]
set_location_assignment PIN_AN19 -to MB_I_OU.a[11]
set_location_assignment PIN_BA17 -to MB_I_OU.a[12]
set_location_assignment PIN_BD17 -to MB_I_OU.a[13]
set_location_assignment PIN_AY18 -to MB_I_OU.act_n
set_location_assignment PIN_AV29 -to MB_I_IN.alert_n
set_location_assignment PIN_BB16 -to MB_I_OU.ba[0]
set_location_assignment PIN_BD16 -to MB_I_OU.ba[1]
set_location_assignment PIN_BC16 -to MB_I_OU.bg[0]
set_location_assignment PIN_AW19 -to MB_I_OU.bg[1]
set_location_assignment PIN_BA15 -to MB_I_OU.a[15]
#set_location_assignment PIN_BC21 -to MB_I_IO.dq[64]
#set_location_assignment PIN_BA22 -to MB_I_IO.dq[65]
#set_location_assignment PIN_BD21 -to MB_I_IO.dq[66]
#set_location_assignment PIN_BB20 -to MB_I_IO.dq[67]
#set_location_assignment PIN_BA20 -to MB_I_IO.dq[68]
#set_location_assignment PIN_BD20 -to MB_I_IO.dq[69]
#set_location_assignment PIN_AY20 -to MB_I_IO.dq[70]
#set_location_assignment PIN_AY22 -to MB_I_IO.dq[71]
set_location_assignment PIN_AU18 -to MB_I_OU.ck[0]
#set_location_assignment PIN_AV18 -to MB_I_OU.ck_n[0]
set_location_assignment PIN_AT16 -to MB_I_OU.ck[1]
#set_location_assignment PIN_AU16 -to MB_I_OU.ck_n[1]
set_location_assignment PIN_BB19 -to MB_I_OU.cke[0]
set_location_assignment PIN_AP16 -to MB_I_OU.cke[1]
set_location_assignment PIN_AY19 -to MB_I_OU.cs_n[0]
set_location_assignment PIN_AN16 -to MB_I_OU.cs_n[1]
set_location_assignment PIN_BC29 -to MB_I_IO.dbi_n[0]
set_location_assignment PIN_AR27 -to MB_I_IO.dbi_n[1]
set_location_assignment PIN_BD24 -to MB_I_IO.dbi_n[2]
set_location_assignment PIN_AM23 -to MB_I_IO.dbi_n[3]
set_location_assignment PIN_AU12 -to MB_I_IO.dbi_n[4]
set_location_assignment PIN_AU13 -to MB_I_IO.dbi_n[5]
set_location_assignment PIN_AM14 -to MB_I_IO.dbi_n[6]
set_location_assignment PIN_AM16 -to MB_I_IO.dbi_n[7]
#set_location_assignment PIN_BA21 -to MB_I_IO.dbi_n[8]
set_location_assignment PIN_BA28 -to MB_I_IO.dqs[0]
set_location_assignment PIN_AM28 -to MB_I_IO.dqs[1]
set_location_assignment PIN_AV24 -to MB_I_IO.dqs[2]
set_location_assignment PIN_AN24 -to MB_I_IO.dqs[3]
set_location_assignment PIN_BC14 -to MB_I_IO.dqs[4]
set_location_assignment PIN_AW14 -to MB_I_IO.dqs[5]
set_location_assignment PIN_AN12 -to MB_I_IO.dqs[6]
set_location_assignment PIN_AK15 -to MB_I_IO.dqs[7]
#set_location_assignment PIN_BC22 -to MB_I_IO.dqs[8]
set_location_assignment PIN_BD19 -to MB_I_OU.odt[0]
set_location_assignment PIN_AR17 -to MB_I_OU.odt[1]
set_location_assignment PIN_BC18 -to MB_I_OU.par
set_location_assignment PIN_BB15 -to MB_I_OU.a[16]
set_location_assignment PIN_AW17 -to MB_I_REF_CLK
set_location_assignment PIN_AV19 -to MB_I_OU.reset_n
set_location_assignment PIN_AY17 -to MB_I_IN.oct_rzqin
set_location_assignment PIN_BC17 -to MB_I_OU.a[14]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cke[1]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cs_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.odt[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_REF_CLK
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.oct_rzqin
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[0]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[1]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[2]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[3]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[4]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[5]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[6]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[7]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[8]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[9]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[10]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[11]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[12]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[13]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.act_n
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.bg[0]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.bg[1]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[15]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[1]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cke[0]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cs_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.par
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[16]
set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_OU.reset_n
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[14]
set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.odt[0]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.alert_n
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[64]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[65]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[66]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[67]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[68]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[69]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[70]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[71]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[0]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[1]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[2]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[3]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[4]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[5]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[6]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[7]
#set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[8]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[7]
#set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[8]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[0]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[1]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[2]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[3]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[4]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[5]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[6]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[7]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[8]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[9]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[10]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[11]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[12]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[13]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[14]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[15]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[16]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[17]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[18]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[19]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[20]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[21]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[22]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[23]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[24]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[25]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[26]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[27]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[28]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[29]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[30]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[31]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[32]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[33]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[34]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[35]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[36]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[37]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[38]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[39]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[40]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[41]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[42]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[43]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[44]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[45]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[46]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[47]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[48]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[49]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[50]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[51]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[52]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[53]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[54]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[55]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[56]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[57]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[58]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[59]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[60]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[61]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[62]
set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[63]
set_location_assignment PIN_M16 -to MB_I_IN.evt
set_location_assignment PIN_AU29 -to MB_I_IO.dq[0]
set_location_assignment PIN_BC28 -to MB_I_IO.dq[1]
set_location_assignment PIN_AY29 -to MB_I_IO.dq[2]
set_location_assignment PIN_BB28 -to MB_I_IO.dq[3]
set_location_assignment PIN_BB29 -to MB_I_IO.dq[4]
set_location_assignment PIN_AW29 -to MB_I_IO.dq[5]
set_location_assignment PIN_BC27 -to MB_I_IO.dq[6]
set_location_assignment PIN_BD29 -to MB_I_IO.dq[7]
set_location_assignment PIN_AR28 -to MB_I_IO.dq[8]
set_location_assignment PIN_AR29 -to MB_I_IO.dq[9]
set_location_assignment PIN_AV27 -to MB_I_IO.dq[10]
set_location_assignment PIN_AU28 -to MB_I_IO.dq[11]
set_location_assignment PIN_AW27 -to MB_I_IO.dq[12]
set_location_assignment PIN_AT28 -to MB_I_IO.dq[13]
set_location_assignment PIN_AV28 -to MB_I_IO.dq[14]
set_location_assignment PIN_AP27 -to MB_I_IO.dq[15]
set_location_assignment PIN_BC24 -to MB_I_IO.dq[16]
set_location_assignment PIN_BB24 -to MB_I_IO.dq[17]
set_location_assignment PIN_BB23 -to MB_I_IO.dq[18]
set_location_assignment PIN_AW22 -to MB_I_IO.dq[19]
set_location_assignment PIN_BA23 -to MB_I_IO.dq[20]
set_location_assignment PIN_BC23 -to MB_I_IO.dq[21]
set_location_assignment PIN_AY23 -to MB_I_IO.dq[22]
set_location_assignment PIN_AY24 -to MB_I_IO.dq[23]
set_location_assignment PIN_AP22 -to MB_I_IO.dq[24]
set_location_assignment PIN_AN23 -to MB_I_IO.dq[25]
set_location_assignment PIN_AR23 -to MB_I_IO.dq[26]
set_location_assignment PIN_AT23 -to MB_I_IO.dq[27]
set_location_assignment PIN_AU23 -to MB_I_IO.dq[28]
set_location_assignment PIN_AV23 -to MB_I_IO.dq[29]
set_location_assignment PIN_AR24 -to MB_I_IO.dq[30]
set_location_assignment PIN_AP24 -to MB_I_IO.dq[31]
set_location_assignment PIN_AV12 -to MB_I_IO.dq[32]
set_location_assignment PIN_AY13 -to MB_I_IO.dq[33]
set_location_assignment PIN_BD14 -to MB_I_IO.dq[34]
set_location_assignment PIN_AY12 -to MB_I_IO.dq[35]
set_location_assignment PIN_BA13 -to MB_I_IO.dq[36]
set_location_assignment PIN_BA12 -to MB_I_IO.dq[37]
set_location_assignment PIN_AW12 -to MB_I_IO.dq[38]
set_location_assignment PIN_BB13 -to MB_I_IO.dq[39]
set_location_assignment PIN_AV13 -to MB_I_IO.dq[40]
set_location_assignment PIN_AR13 -to MB_I_IO.dq[41]
set_location_assignment PIN_AR15 -to MB_I_IO.dq[42]
set_location_assignment PIN_AP15 -to MB_I_IO.dq[43]
set_location_assignment PIN_AT15 -to MB_I_IO.dq[44]
set_location_assignment PIN_AU14 -to MB_I_IO.dq[45]
set_location_assignment PIN_AU15 -to MB_I_IO.dq[46]
set_location_assignment PIN_AV14 -to MB_I_IO.dq[47]
set_location_assignment PIN_AM13 -to MB_I_IO.dq[48]
set_location_assignment PIN_AT13 -to MB_I_IO.dq[49]
set_location_assignment PIN_AT12 -to MB_I_IO.dq[50]
set_location_assignment PIN_AP14 -to MB_I_IO.dq[51]
set_location_assignment PIN_AN13 -to MB_I_IO.dq[52]
set_location_assignment PIN_AK13 -to MB_I_IO.dq[53]
set_location_assignment PIN_AM12 -to MB_I_IO.dq[54]
set_location_assignment PIN_AL13 -to MB_I_IO.dq[55]
set_location_assignment PIN_AH13 -to MB_I_IO.dq[56]
set_location_assignment PIN_AL15 -to MB_I_IO.dq[57]
set_location_assignment PIN_AM15 -to MB_I_IO.dq[58]
set_location_assignment PIN_AJ14 -to MB_I_IO.dq[59]
set_location_assignment PIN_AJ12 -to MB_I_IO.dq[60]
set_location_assignment PIN_AL16 -to MB_I_IO.dq[61]
set_location_assignment PIN_AK12 -to MB_I_IO.dq[62]
set_location_assignment PIN_AH14 -to MB_I_IO.dq[63]
set_location_assignment PIN_AY28 -to MB_I_IO.dqs_n[0]
set_location_assignment PIN_AN28 -to MB_I_IO.dqs_n[1]
set_location_assignment PIN_AU24 -to MB_I_IO.dqs_n[2]
set_location_assignment PIN_AM24 -to MB_I_IO.dqs_n[3]
set_location_assignment PIN_BB14 -to MB_I_IO.dqs_n[4]
set_location_assignment PIN_AY14 -to MB_I_IO.dqs_n[5]
set_location_assignment PIN_AP12 -to MB_I_IO.dqs_n[6]
set_location_assignment PIN_AK14 -to MB_I_IO.dqs_n[7]
#set_location_assignment PIN_BD22 -to MB_I_IO.dqs_n[8]
boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G_I/tb_unb2c_test_ddr_16G_I.vhd 0 → 100644
+ 35
− 0
View file @ 7d055f4b
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr_16G_I is
end tb_unb2c_test_ddr_16G_I;
architecture tb of tb_unb2c_test_ddr_16G_I is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
generic map (
g_design_name => "unb2c_test_ddr_16G_I"
);
end tb;
boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G_I/unb2c_test_ddr_16G_I.vhd 0 → 100644
+ 125
− 0
View file @ 7d055f4b
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr_16G_I is
generic (
g_design_name : string := "unb2c_test_ddr_16G_I";
g_design_note : string := "DDR: MB I";
g_sim : boolean := false; -- Overridden by TB
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : string := "" -- revision ID -- set by QSF
);
port (
-- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
INTB : inout std_logic; -- FPGA interconnect line
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
MB_II_IN : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0)
);
end unb2c_test_ddr_16G_I;
architecture str of unb2c_test_ddr_16G_I is
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_revision_id => g_revision_id
)
port map (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- DDR reference clocks
MB_I_REF_CLK => MB_I_REF_CLK,
MB_II_REF_CLK => MB_II_REF_CLK,
-- SO-DIMM Memory Bank I
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU,
-- SO-DIMM Memory Bank II
MB_II_IN => MB_II_IN,
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU,
QSFP_LED => QSFP_LED
);
end str;
boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+ 26
− 7
View file @ 7d055f4b
......@@ -128,6 +128,7 @@ architecture str of unb2c_test is
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_125M;
constant c_dp_clk_freq : natural := c_unb2c_board_ext_clk_freq_200M;
-- Revision controlled constants
constant c_revision_select : t_unb2c_test_config := func_sel_revision_rec(g_design_name);
......@@ -438,6 +439,12 @@ architecture str of unb2c_test is
signal ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
signal ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
-- DDR calibration_ok signals are set to '1' by default such that the corresponding
-- LED is turned ON when no IP is instantiated. This is prefered over turning it off
-- as that would indicate a (false) calibration error.
signal ddr_I_cal_ok : std_logic := '1';
signal ddr_II_cal_ok : std_logic := '1';
-- UDP streaming ports for 1GbE I and 1GbE II
-- . eth_0 = 1GbE I
signal gn_eth_src_mac_I : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
......@@ -1236,16 +1243,22 @@ begin
QSFP_LED => QSFP_LED
);
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds_v2
generic map (
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
g_mm_pulse_us => 1000 / (10**9 / c_mm_clk_freq),
g_dp_pulse_us => 1000 / (10**9 / c_dp_clk_freq)
)
port map (
rst => mm_rst,
clk => mm_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => dp_pps,
ddr_I_cal_ok => ddr_I_cal_ok,
ddr_II_cal_ok => ddr_II_cal_ok,
green_led_arr => qsfp_green_led_arr,
red_led_arr => qsfp_red_led_arr
);
......@@ -1312,6 +1325,9 @@ begin
phy4_io => MB_I_IO,
phy4_ou => MB_I_OU,
-- DDR4 Calibration result for LED indicator
ddr_cal_ok => ddr_I_cal_ok,
---------------------------------------------------------------------------
-- DIAG Tx seq
---------------------------------------------------------------------------
......@@ -1389,6 +1405,9 @@ begin
phy4_io => MB_II_IO,
phy4_ou => MB_II_OU,
-- DDR4 Calibration result for LED indicator
ddr_cal_ok => ddr_II_cal_ok,
---------------------------------------------------------------------------
-- DIAG Tx seq
---------------------------------------------------------------------------
......
boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+ 2
− 0
View file @ 7d055f4b
......@@ -84,6 +84,7 @@ package unb2c_test_pkg is
constant c_test_10GbE_qb : t_unb2c_test_config := (false,false,false, true,false, true,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
constant c_test_ddr : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
constant c_test_ddr_16G : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
constant c_test_ddr_16G_I : t_unb2c_test_config := (false,false,false,false,false,false,false, true,false,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
constant c_test_heater : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false, true,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
......@@ -102,6 +103,7 @@ package body unb2c_test_pkg is
elsif g_design_name = "unb2c_test_1GbE_I" then return c_test_1GbE_I_UDP;
elsif g_design_name = "unb2c_test_1GbE_II" then return c_test_1GbE_II_UDP;
elsif g_design_name = "unb2c_test_ddr_16G" then return c_test_ddr_16G;
elsif g_design_name = "unb2c_test_ddr_16G_I" then return c_test_ddr_16G_I;
else return c_test_minimal;
end if;
......
libraries/io/ddr/src/vhdl/io_ddr.vhd
+ 6
− 2
View file @ 7d055f4b
......@@ -223,7 +223,10 @@ entity io_ddr is
-- DDR4 PHY external interface
phy4_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
phy4_io : inout t_tech_ddr4_phy_io;
phy4_ou : out t_tech_ddr4_phy_ou
phy4_ou : out t_tech_ddr4_phy_ou;
-- DDR Calibration result
ddr_cal_ok : out std_logic := '0'
);
end io_ddr;
......@@ -492,6 +495,7 @@ begin
);
ctlr_rst_out <= ctlr_rst_out_i;
ddr_cal_ok <= ctlr_tech_miso.done;
u_wr_fifo_full : entity common_lib.common_switch
generic map(
......
libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
+ 7
− 2
View file @ 7d055f4b
......@@ -90,7 +90,10 @@ entity mms_io_ddr is
-- DDR4 PHY external interface
phy4_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
phy4_io : inout t_tech_ddr4_phy_io;
phy4_ou : out t_tech_ddr4_phy_ou
phy4_ou : out t_tech_ddr4_phy_ou;
-- DDR Calibration result
ddr_cal_ok : out std_logic := '0'
);
end mms_io_ddr;
......@@ -181,7 +184,9 @@ begin
phy4_in => phy4_in,
phy4_io => phy4_io,
phy4_ou => phy4_ou
phy4_ou => phy4_ou,
ddr_cal_ok => ddr_cal_ok
);
-- MM register map for DDR controller write and read access control via MM
......
libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
+ 7
− 1
View file @ 7d055f4b
......@@ -117,6 +117,9 @@ entity mms_io_ddr_diag is
phy4_io : inout t_tech_ddr4_phy_io;
phy4_ou : out t_tech_ddr4_phy_ou;
-- DDR Calibration result
ddr_cal_ok : out std_logic := '0';
---------------------------------------------------------------------------
-- DIAG Tx seq
---------------------------------------------------------------------------
......@@ -213,7 +216,10 @@ begin
-- DDR4 PHY external interface
phy4_in => phy4_in,
phy4_io => phy4_io,
phy4_ou => phy4_ou
phy4_ou => phy4_ou,
-- DDR Calibration result
ddr_cal_ok => ddr_cal_ok
);
-----------------------------------------------------------------------------
......
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