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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd

@@ -34,15 +34,15 @@ USE dp_lib.dp_stream_pkg.ALL;
 ENTITY ddrctrl_pack IS
   GENERIC (
 
-    g_nof_streams	: POSITIVE := 12;
-    g_data_w		  : NATURAL  := 14
+    g_nof_streams	: POSITIVE := 12;                                                             -- number of input streams
+    g_data_w		  : NATURAL  := 14                                                              -- data with of input data vectors
 
   );
   PORT (
 
-    clk	      	  : IN  STD_LOGIC;
-    in_sosi_arr   : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-    out_data 	    : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
+    clk	      	  : IN  STD_LOGIC;                                                              -- clock signal
+    in_sosi_arr   : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);                                 -- input signal
+    out_data 	    : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)                   -- output signal
 
   );
 END ddrctrl_pack;
@@ -51,6 +51,7 @@ ARCHITECTURE rtl OF ddrctrl_pack IS
 
 BEGIN
 
+  -- Putting all the data from the different streams into one data vector.
   gen_extract_and_pack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
     out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
   END GENERATE;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd

@@ -35,9 +35,8 @@ USE common_lib.common_pkg.ALL;
 ENTITY tb_ddrctrl_pack IS
   GENERIC (
 
-    g_nof_streams             : POSITIVE                                := 12;
-    g_data_w                  : NATURAL                                 := 14;
-    g_sim_model               : BOOLEAN                                 := TRUE
+    g_nof_streams             : POSITIVE                                := 12;                                    -- number of input streams
+    g_data_w                  : NATURAL                                 := 14;                                    -- data with of input data vectors
 
   );
 END tb_ddrctrl_pack;
@@ -45,60 +44,68 @@ END tb_ddrctrl_pack;
 ARCHITECTURE tb OF tb_ddrctrl_pack IS
 
   CONSTANT  c_clk_freq        : NATURAL                                     := 200;                               -- MHz
-  CONSTANT  c_clk_period      : TIME                                    := (10**6 / c_clk_freq) * 1 ps;
+  CONSTANT  c_clk_period      : TIME                                        := (10**6 / c_clk_freq) * 1 ps;       -- clock priod, 5 ns
 
-  CONSTANT  c_data_w          : NATURAL                                 := g_nof_streams * g_data_w; -- 168
+
+  CONSTANT  c_out_data_w      : NATURAL                                     := g_nof_streams * g_data_w;          -- output data with, 168
 
   FUNCTION c_testv_init RETURN STD_LOGIC_VECTOR IS
-    VARIABLE temp : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+    VARIABLE temp : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
   BEGIN
     FOR I IN 0 TO g_nof_streams-1 LOOP
       temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
     END LOOP;
     RETURN temp;
   END FUNCTION c_testv_init;
-  CONSTANT  c_testv           : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0)   := c_testv_init;
+  CONSTANT  c_testv           : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0)   := c_testv_init;                      -- testvector which contains a number for each stream, so the data of stream 6 will look like ...00110
+
+
 
+  SIGNAL    tb_end            : STD_LOGIC                                   := '0';                               -- signal to turn the testbench off
 
-  SIGNAL    tb_end            : STD_LOGIC                               := '0';
 
-  SIGNAL    clk               : STD_LOGIC                               := '1';
-  SIGNAL    in_sosi_arr       : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init);
+  SIGNAL    clk               : STD_LOGIC                                   := '1';                               -- clock signal
+  SIGNAL    in_sosi_arr       : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)     := (OTHERS => c_dp_sosi_init);        -- input signal for ddrctrl_pack.vhd 
 
-  SIGNAL    out_data          : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+  SIGNAL    out_data          : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);                                        -- output signal from ddrctrl_pack.vhd
 
 BEGIN
 
-  clk               <= NOT clk OR tb_end AFTER c_clk_period/2;
+  clk               <= NOT clk OR tb_end AFTER c_clk_period/2;                                                    -- generating clock signal
 
   p_mm : PROCESS
   BEGIN
 
+    -- Start the testbench.
     tb_end            <= '0';
-
     WAIT UNTIL rising_edge(clk);  -- align to rising edge
     WAIT FOR c_clk_period*2;
 
+
+    -- The input data vectors get filled with the corresponding number.
     fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
       in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0)   <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
     END LOOP;
 
 
+    -- The numbers get cycled trough the input vectors.
     change_in_sosi_arr : FOR J IN 0 TO 4 LOOP
       WAIT FOR c_clk_period*1;
       in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0)   <= in_sosi_arr(g_nof_streams-1).data(g_data_w - 1 DOWNTO 0);
-      gen_switch_data : FOR I IN 1 TO g_nof_streams-1 LOOP
+      loop_switch_data : FOR I IN 0 TO g_nof_streams-1 LOOP
         in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= in_sosi_arr(I-1).data(g_data_w - 1 DOWNTO 0);
       END LOOP;
     END LOOP;  
 
+    -- Stop the testbench.
     WAIT FOR c_clk_period*4;
-
     tb_end <= '1';
 
+
     WAIT;
   END PROCESS;
 
+  -- Verification by checking if the input vectors equel the corresponding index of the output vector. 
   p_verify : PROCESS
   BEGIN
     WAIT UNTIL rising_edge(clk);
@@ -109,6 +116,8 @@ BEGIN
     END IF;
   END PROCESS;
 
+
+
   u_ddrctrl_pack : ENTITY work.ddrctrl_pack
   GENERIC MAP (
     g_nof_streams     => g_nof_streams,