From 7c4c80d1363270c905ae70fd94798aa075cdc4fc Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 19 Dec 2014 16:15:39 +0000
Subject: [PATCH] Added ddr3 memory model for simulation. The model comes from
an example design in ip_stratixivdiff
---
libraries/technology/ddr/hdllib.cfg | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 7d51fce5d3..3b43e2b204 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_ddr
hdl_library_clause_name = tech_ddr_lib
-hdl_lib_uses = common
+hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_mem_model common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
@@ -13,3 +13,5 @@ synth_files =
tech_ddr.vhd
test_bench_files =
+ tech_ddr_mem_model_component_pkg.vhd
+ tech_ddr_mem_model.vhd
--
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