Added desccription. Only report simulation finished, not whether it finished...

Added desccription. Only report simulation finished, not whether it finished with or without errors.

libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd

@@ -20,6 +20,12 @@
 --
 -------------------------------------------------------------------------------
 
+-- Purpose: Testbench for eth_ihl_to_20.vhd
+-- Description:
+-- Usage:
+--   > as 10
+--   > run -all
+
 LIBRARY IEEE, common_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
@@ -218,7 +224,7 @@ BEGIN
     END LOOP;
     
     WAIT for 1 us;
-    ASSERT FALSE REPORT "Simulation finished: NO ERRORS" SEVERITY FAILURE;
+    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
     WAIT;
   END PROCESS;