From 79a184a4c7eb9341fe34c50c3beb34a78ca760c9 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 13 Jun 2014 10:02:51 +0000
Subject: [PATCH] Added desccription. Only report simulation finished, not
whether it finished with or without errors.
---
libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
index 683990729a..96071c42d3 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
@@ -20,6 +20,12 @@
--
-------------------------------------------------------------------------------
+-- Purpose: Testbench for eth_ihl_to_20.vhd
+-- Description:
+-- Usage:
+-- > as 10
+-- > run -all
+
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
@@ -218,7 +224,7 @@ BEGIN
END LOOP;
WAIT for 1 us;
- ASSERT FALSE REPORT "Simulation finished: NO ERRORS" SEVERITY FAILURE;
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
--
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