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Commit 8b5e8b99 authored by Eric Kooistra's avatar Eric Kooistra
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Added description. Added tb_end. Also verify rx_pkt_cnt.

parent e8fc980f
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...@@ -20,6 +20,26 @@ ...@@ -20,6 +20,26 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Purpose: Testbench for eth
-- Description:
--
-- The p_lcu_transmitter transmits packets and the p_eth_control loops them
-- back to p_lcu_receiver:
--
-- ------- -------
-- /---| |<---| |<--- p_lcu_transmitter
-- p_eth_control | | DUT | | LCU |
-- \-->|(ETH)|--->|(TSE)|---> p_lcu_receiver
-- ------- -------
--
-- The tb is self checking based on:
-- . proc_tse_rx_packet() for expected header and data type
-- . tx_pkt_cnt=rx_pkt_cnt > 0 must be true at the tb_end.
-- Usage:
-- > as 10
-- > run -all
LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib; LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
...@@ -48,9 +68,6 @@ END tb_eth; ...@@ -48,9 +68,6 @@ END tb_eth;
ARCHITECTURE tb OF tb_eth IS ARCHITECTURE tb OF tb_eth IS
-- as 10
-- run 100 us
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT cable_delay : TIME := 12 ns; CONSTANT cable_delay : TIME := 12 ns;
...@@ -186,6 +203,7 @@ ARCHITECTURE tb OF tb_eth IS ...@@ -186,6 +203,7 @@ ARCHITECTURE tb OF tb_eth IS
CONSTANT c_dut_control_tx_en : NATURAL := 2**c_eth_mm_reg_control_bi.tx_en; CONSTANT c_dut_control_tx_en : NATURAL := 2**c_eth_mm_reg_control_bi.tx_en;
-- Clocks and reset -- Clocks and reset
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL eth_clk : STD_LOGIC := '0'; -- tse reference clock SIGNAL eth_clk : STD_LOGIC := '0'; -- tse reference clock
SIGNAL sys_clk : STD_LOGIC := '0'; -- system clock SIGNAL sys_clk : STD_LOGIC := '0'; -- system clock
SIGNAL st_clk : STD_LOGIC; -- stream clock SIGNAL st_clk : STD_LOGIC; -- stream clock
...@@ -238,6 +256,10 @@ ARCHITECTURE tb OF tb_eth IS ...@@ -238,6 +256,10 @@ ARCHITECTURE tb OF tb_eth IS
SIGNAL lcu_rxp : STD_LOGIC; SIGNAL lcu_rxp : STD_LOGIC;
SIGNAL lcu_led : t_tse_led; SIGNAL lcu_led : t_tse_led;
-- Verification
SIGNAL tx_pkt_cnt : NATURAL := 0;
SIGNAL rx_pkt_cnt : NATURAL := 0;
BEGIN BEGIN
-- run 50 us -- run 50 us
...@@ -427,6 +449,8 @@ BEGIN ...@@ -427,6 +449,8 @@ BEGIN
-- proc_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi); -- proc_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi); -- proc_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
FOR I IN 0 TO 1500 * 5 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
...@@ -493,7 +517,7 @@ BEGIN ...@@ -493,7 +517,7 @@ BEGIN
tse_led => eth_led tse_led => eth_led
); );
lcu : ENTITY work.tse lcu : ENTITY tech_tse_lib.tech_tse
PORT MAP ( PORT MAP (
-- Clocks and reset -- Clocks and reset
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -528,4 +552,26 @@ BEGIN ...@@ -528,4 +552,26 @@ BEGIN
tse_led => lcu_led tse_led => lcu_led
); );
-- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN lcu_tx_sosi.sop='1' AND rising_edge(st_clk);
rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN lcu_rx_sosi.eop='1' AND rising_edge(st_clk);
p_tb_end : PROCESS
BEGIN
WAIT UNTIL tb_end='1';
-- Verify that all transmitted packets have been received
IF tx_pkt_cnt=0 THEN
REPORT "No packets were transmitted." SEVERITY ERROR;
ELSIF rx_pkt_cnt=0 THEN
REPORT "No packets were received." SEVERITY ERROR;
ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
REPORT "Not all transmitted packets were received." SEVERITY ERROR;
END IF;
-- Stop the simulation
ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
END tb; END tb;
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