Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
8b5e8b99
Commit
8b5e8b99
authored
10 years ago
by
Eric Kooistra
Browse files
Options
Downloads
Patches
Plain Diff
Added description. Added tb_end. Also verify rx_pkt_cnt.
parent
e8fc980f
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
libraries/io/eth/tb/vhdl/tb_eth.vhd
+50
-4
50 additions, 4 deletions
libraries/io/eth/tb/vhdl/tb_eth.vhd
with
50 additions
and
4 deletions
libraries/io/eth/tb/vhdl/tb_eth.vhd
+
50
−
4
View file @
8b5e8b99
...
@@ -20,6 +20,26 @@
...
@@ -20,6 +20,26 @@
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Purpose: Testbench for eth
-- Description:
--
-- The p_lcu_transmitter transmits packets and the p_eth_control loops them
-- back to p_lcu_receiver:
--
-- ------- -------
-- /---| |<---| |<--- p_lcu_transmitter
-- p_eth_control | | DUT | | LCU |
-- \-->|(ETH)|--->|(TSE)|---> p_lcu_receiver
-- ------- -------
--
-- The tb is self checking based on:
-- . proc_tse_rx_packet() for expected header and data type
-- . tx_pkt_cnt=rx_pkt_cnt > 0 must be true at the tb_end.
-- Usage:
-- > as 10
-- > run -all
LIBRARY
IEEE
,
common_lib
,
dp_lib
,
tech_tse_lib
;
LIBRARY
IEEE
,
common_lib
,
dp_lib
,
tech_tse_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
numeric_std
.
ALL
;
USE
IEEE
.
numeric_std
.
ALL
;
...
@@ -48,9 +68,6 @@ END tb_eth;
...
@@ -48,9 +68,6 @@ END tb_eth;
ARCHITECTURE
tb
OF
tb_eth
IS
ARCHITECTURE
tb
OF
tb_eth
IS
-- as 10
-- run 100 us
CONSTANT
sys_clk_period
:
TIME
:
=
10
ns
;
-- 100 MHz
CONSTANT
sys_clk_period
:
TIME
:
=
10
ns
;
-- 100 MHz
CONSTANT
eth_clk_period
:
TIME
:
=
8
ns
;
-- 125 MHz
CONSTANT
eth_clk_period
:
TIME
:
=
8
ns
;
-- 125 MHz
CONSTANT
cable_delay
:
TIME
:
=
12
ns
;
CONSTANT
cable_delay
:
TIME
:
=
12
ns
;
...
@@ -186,6 +203,7 @@ ARCHITECTURE tb OF tb_eth IS
...
@@ -186,6 +203,7 @@ ARCHITECTURE tb OF tb_eth IS
CONSTANT
c_dut_control_tx_en
:
NATURAL
:
=
2
**
c_eth_mm_reg_control_bi
.
tx_en
;
CONSTANT
c_dut_control_tx_en
:
NATURAL
:
=
2
**
c_eth_mm_reg_control_bi
.
tx_en
;
-- Clocks and reset
-- Clocks and reset
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
eth_clk
:
STD_LOGIC
:
=
'0'
;
-- tse reference clock
SIGNAL
eth_clk
:
STD_LOGIC
:
=
'0'
;
-- tse reference clock
SIGNAL
sys_clk
:
STD_LOGIC
:
=
'0'
;
-- system clock
SIGNAL
sys_clk
:
STD_LOGIC
:
=
'0'
;
-- system clock
SIGNAL
st_clk
:
STD_LOGIC
;
-- stream clock
SIGNAL
st_clk
:
STD_LOGIC
;
-- stream clock
...
@@ -238,6 +256,10 @@ ARCHITECTURE tb OF tb_eth IS
...
@@ -238,6 +256,10 @@ ARCHITECTURE tb OF tb_eth IS
SIGNAL
lcu_rxp
:
STD_LOGIC
;
SIGNAL
lcu_rxp
:
STD_LOGIC
;
SIGNAL
lcu_led
:
t_tse_led
;
SIGNAL
lcu_led
:
t_tse_led
;
-- Verification
SIGNAL
tx_pkt_cnt
:
NATURAL
:
=
0
;
SIGNAL
rx_pkt_cnt
:
NATURAL
:
=
0
;
BEGIN
BEGIN
-- run 50 us
-- run 50 us
...
@@ -427,6 +449,8 @@ BEGIN
...
@@ -427,6 +449,8 @@ BEGIN
-- proc_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
FOR
I
IN
0
TO
1500
*
5
LOOP
WAIT
UNTIL
rising_edge
(
st_clk
);
END
LOOP
;
tb_end
<=
'1'
;
WAIT
;
WAIT
;
END
PROCESS
;
END
PROCESS
;
...
@@ -493,7 +517,7 @@ BEGIN
...
@@ -493,7 +517,7 @@ BEGIN
tse_led
=>
eth_led
tse_led
=>
eth_led
);
);
lcu
:
ENTITY
work
.
tse
lcu
:
ENTITY
tech_tse_lib
.
tech_
tse
PORT
MAP
(
PORT
MAP
(
-- Clocks and reset
-- Clocks and reset
mm_rst
=>
mm_rst
,
mm_rst
=>
mm_rst
,
...
@@ -528,4 +552,26 @@ BEGIN
...
@@ -528,4 +552,26 @@ BEGIN
tse_led
=>
lcu_led
tse_led
=>
lcu_led
);
);
-- Verification
tx_pkt_cnt
<=
tx_pkt_cnt
+
1
WHEN
lcu_tx_sosi
.
sop
=
'1'
AND
rising_edge
(
st_clk
);
rx_pkt_cnt
<=
rx_pkt_cnt
+
1
WHEN
lcu_rx_sosi
.
eop
=
'1'
AND
rising_edge
(
st_clk
);
p_tb_end
:
PROCESS
BEGIN
WAIT
UNTIL
tb_end
=
'1'
;
-- Verify that all transmitted packets have been received
IF
tx_pkt_cnt
=
0
THEN
REPORT
"No packets were transmitted."
SEVERITY
ERROR
;
ELSIF
rx_pkt_cnt
=
0
THEN
REPORT
"No packets were received."
SEVERITY
ERROR
;
ELSIF
tx_pkt_cnt
/=
rx_pkt_cnt
THEN
REPORT
"Not all transmitted packets were received."
SEVERITY
ERROR
;
END
IF
;
-- Stop the simulation
ASSERT
FALSE
REPORT
"Simulation finished."
SEVERITY
FAILURE
;
WAIT
;
END
PROCESS
;
END
tb
;
END
tb
;
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment