-Fixed multiple signal assignment by taking adder instances out of generate loop.

libraries/base/dp/src/vhdl/dp_complex_add.vhd

@@ -65,11 +65,11 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Complex Adder Trees
   -----------------------------------------------------------------------------
-  gen_common_complex_mult : FOR i IN 0 TO g_nof_inputs-1 GENERATE
-
+  gen_nof_inputs : FOR i IN 0 TO g_nof_inputs-1 GENERATE
     -- DP SOSI array to flat STD_LOGIC_VECTORs
     common_adder_tree_re_in_dat((i+1)*g_data_w-1 DOWNTO i*g_data_w) <= snk_in_arr(i).re(g_data_w-1 DOWNTO 0);
     common_adder_tree_im_in_dat((i+1)*g_data_w-1 DOWNTO i*g_data_w) <= snk_in_arr(i).im(g_data_w-1 DOWNTO 0);
+  END GENERATE;
 
   -- One adder tree for the real part
   u_adder_tree_re : ENTITY common_lib.common_adder_tree(str) 
@@ -101,8 +101,6 @@ BEGIN
     sum    => common_adder_tree_im_sum
   );   
 
-  END GENERATE;
-
   src_out.re <= RESIZE_DP_DSP_DATA(common_adder_tree_re_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
   src_out.im <= RESIZE_DP_DSP_DATA(common_adder_tree_im_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));