From 77703a59a3d95f28f30d4a89b115b57f86708e81 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Thu, 20 Jul 2017 12:08:01 +0000
Subject: [PATCH] -Fixed multiple signal assignment by taking adder instances
 out of generate loop.

---
 libraries/base/dp/src/vhdl/dp_complex_add.vhd | 64 +++++++++----------
 1 file changed, 31 insertions(+), 33 deletions(-)

diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
index 0544a30a3c..951c94264f 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_add.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -65,44 +65,42 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Complex Adder Trees
   -----------------------------------------------------------------------------
-  gen_common_complex_mult : FOR i IN 0 TO g_nof_inputs-1 GENERATE
-
+  gen_nof_inputs : FOR i IN 0 TO g_nof_inputs-1 GENERATE
     -- DP SOSI array to flat STD_LOGIC_VECTORs
     common_adder_tree_re_in_dat((i+1)*g_data_w-1 DOWNTO i*g_data_w) <= snk_in_arr(i).re(g_data_w-1 DOWNTO 0);
     common_adder_tree_im_in_dat((i+1)*g_data_w-1 DOWNTO i*g_data_w) <= snk_in_arr(i).im(g_data_w-1 DOWNTO 0);
-
-    -- One adder tree for the real part
-    u_adder_tree_re : ENTITY common_lib.common_adder_tree(str) 
-    GENERIC MAP (
-      g_representation => "SIGNED",
-      g_pipeline       => c_pipeline,          
-      g_nof_inputs     => g_nof_inputs,
-      g_dat_w          => g_data_w,
-      g_sum_w          => c_common_adder_tree_sum_w 
-    )
-    PORT MAP (
-      clk    => clk,
-      in_dat => common_adder_tree_re_in_dat,
-      sum    => common_adder_tree_re_sum
-    );
-    
-    -- One adder tree for the imaginary part
-    u_adder_tree_im : ENTITY common_lib.common_adder_tree(str) 
-    GENERIC MAP (
-      g_representation => "SIGNED",
-      g_pipeline       => c_pipeline,          
-      g_nof_inputs     => g_nof_inputs,
-      g_dat_w          => g_data_w,
-      g_sum_w          => c_common_adder_tree_sum_w 
-    )
-    PORT MAP (
-      clk    => clk,
-      in_dat => common_adder_tree_im_in_dat,
-      sum    => common_adder_tree_im_sum
-    );   
-
   END GENERATE;
 
+  -- One adder tree for the real part
+  u_adder_tree_re : ENTITY common_lib.common_adder_tree(str) 
+  GENERIC MAP (
+    g_representation => "SIGNED",
+    g_pipeline       => c_pipeline,          
+    g_nof_inputs     => g_nof_inputs,
+    g_dat_w          => g_data_w,
+    g_sum_w          => c_common_adder_tree_sum_w 
+  )
+  PORT MAP (
+    clk    => clk,
+    in_dat => common_adder_tree_re_in_dat,
+    sum    => common_adder_tree_re_sum
+  );
+  
+  -- One adder tree for the imaginary part
+  u_adder_tree_im : ENTITY common_lib.common_adder_tree(str) 
+  GENERIC MAP (
+    g_representation => "SIGNED",
+    g_pipeline       => c_pipeline,          
+    g_nof_inputs     => g_nof_inputs,
+    g_dat_w          => g_data_w,
+    g_sum_w          => c_common_adder_tree_sum_w 
+  )
+  PORT MAP (
+    clk    => clk,
+    in_dat => common_adder_tree_im_in_dat,
+    sum    => common_adder_tree_im_sum
+  );   
+
   src_out.re <= RESIZE_DP_DSP_DATA(common_adder_tree_re_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
   src_out.im <= RESIZE_DP_DSP_DATA(common_adder_tree_im_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
 
-- 
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