Added sim_dbg_status to ease viewing out_status fields in wave window.

libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd

@@ -169,6 +169,16 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
   SIGNAL dbg_c_wb_fifo_latency      : NATURAL := c_wb_fifo_latency;
   SIGNAL dbg_c_wb_fifo_fill_min     : NATURAL := c_wb_fifo_fill_min;
   
+  SIGNAL dbg_status_0_out_word_locked       : STD_LOGIC;
+  SIGNAL dbg_status_1_out_word_stable       : STD_LOGIC;
+  SIGNAL dbg_status_4_dp_phs_locked         : STD_LOGIC;
+  SIGNAL dbg_status_6_dp_in_clk_detected    : STD_LOGIC;
+  SIGNAL dbg_status_7_dp_in_clk_stable      : STD_LOGIC;
+  SIGNAL dbg_status_15_8_fifo_rdusedw       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL dbg_status_23_16_wb_cnt_latency    : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL dbg_status_27_24_dp_phs_clk_select : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL dbg_status_31_28_dp_raw_phs        : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  
   -- in_clk domain
   TYPE t_in_reg IS RECORD
     -- data with realignment
@@ -185,6 +195,9 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
     fifo_wr_req_p       : STD_LOGIC;
   END RECORD;
   
+  SIGNAL i_out_status        : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL i_out_word_stable   : STD_LOGIC;
+  
   SIGNAL in_rst              : STD_LOGIC;
   SIGNAL in_fifo_wr_dat      : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
   SIGNAL in_fifo_wr_req      : STD_LOGIC;
@@ -697,26 +710,41 @@ BEGIN
   p_out_status : PROCESS(r_dp, dp_in_clk_stable, dp_in_clk_detected, fifo_rdusedw)
   BEGIN
     -- Debug monitor status
-    out_status               <= (OTHERS=>'0');
-    out_status(           4) <= r_dp.dp_phs_locked;                     -- 1 bit
-    out_status( 7 DOWNTO  6) <= dp_in_clk_stable & dp_in_clk_detected;  -- 2 bit
-    out_status(15 DOWNTO  8) <= fifo_rdusedw;                           -- c_fifo_size_w = 8
-    out_status(23 DOWNTO 16) <= RESIZE_UVEC(r_dp.wb_cnt_latency, 8);    -- c_wb_cnt_w <= 8
-    out_status(27 DOWNTO 24) <= TO_UVEC(r_dp.dp_phs_clk_select, 4);     -- g_nof_dp_phs_clk <= 6, fits in 4 bit
-    out_status(31 DOWNTO 28) <= r_dp.dp_raw_phs;                        -- g_wb_factor = 4
+    i_out_status               <= (OTHERS=>'0');
+    i_out_status(           4) <= r_dp.dp_phs_locked;                     -- 1 bit
+    i_out_status( 7 DOWNTO  6) <= dp_in_clk_stable & dp_in_clk_detected;  -- 2 bit
+    i_out_status(15 DOWNTO  8) <= fifo_rdusedw;                           -- c_fifo_size_w = 8
+    i_out_status(23 DOWNTO 16) <= RESIZE_UVEC(r_dp.wb_cnt_latency, 8);    -- c_wb_cnt_w <= 8
+    i_out_status(27 DOWNTO 24) <= TO_UVEC(r_dp.dp_phs_clk_select, 4);     -- g_nof_dp_phs_clk <= 6, fits in 4 bit
+    i_out_status(31 DOWNTO 28) <= r_dp.dp_raw_phs;                        -- g_wb_factor = 4
   END PROCESS;
   
+  out_status <= i_out_status;
+  
+  sim_dbg_status : IF g_sim=TRUE GENERATE 
+    dbg_status_0_out_word_locked       <= r_dp.dp_word_locked;
+    dbg_status_1_out_word_stable       <= i_out_word_stable;
+    dbg_status_4_dp_phs_locked         <= i_out_status(4);
+    dbg_status_6_dp_in_clk_detected    <= i_out_status(6);
+    dbg_status_7_dp_in_clk_stable      <= i_out_status(7);
+    dbg_status_15_8_fifo_rdusedw       <= i_out_status(15 DOWNTO 8);
+    dbg_status_23_16_wb_cnt_latency    <= i_out_status(23 DOWNTO 16);
+    dbg_status_27_24_dp_phs_clk_select <= i_out_status(27 DOWNTO 24);
+    dbg_status_31_28_dp_raw_phs        <= i_out_status(31 DOWNTO 28) WHEN r_dp.dp_val='1' AND r_dp.le_val='1';  -- latch to view only yhe raw_phs when in lock
+  END GENERATE;
+  
   u_common_stable_monitor : ENTITY common_lib.common_stable_monitor
   PORT MAP (
     rst          => dp_rst,
     clk          => dp_clk,
     -- MM
     r_in         => r_dp.dp_word_locked,
-    r_stable     => out_word_stable,
+    r_stable     => i_out_word_stable,
     r_stable_ack => out_word_stable_ack
   );
     
   out_word_locked <= r_dp.dp_word_locked;
+  out_word_stable <= i_out_word_stable;
   
   ------------------------------------------------------------------------------
   -- Registers