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Commit 73b66c59 authored by Reinier van der Walle's avatar Reinier van der Walle
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processed review comments; Improved dp_sync_recover restart process.

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1 merge request!111added tb for dp_sync_recover and added restart signal to bsn_source_v2
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with 100 additions and 67 deletions
applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+ 3
− 3
View file @ 73b66c59
......@@ -125,7 +125,7 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
SIGNAL rx_sysref : STD_LOGIC;
SIGNAL arst : STD_LOGIC;
SIGNAL i_dp_bsn_source_restart : STD_LOGIC;
SIGNAL rx_bsn_source_restart : STD_LOGIC;
-- Sosis and sosi arrays
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
......@@ -258,7 +258,7 @@ BEGIN
-- Streaming clock domain
bs_sosi => bs_sosi,
restart => i_dp_bsn_source_restart
bs_restart => rx_bsn_source_restart
);
u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
......@@ -478,7 +478,7 @@ BEGIN
PORT MAP (
rst => arst,
wr_clk => rx_clk,
wr_dat(0) => i_dp_bsn_source_restart,
wr_dat(0) => rx_bsn_source_restart,
wr_req => bs_sosi.valid,
rd_clk => dp_clk,
rd_dat(0) => dp_bsn_source_restart,
......
applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+ 9
− 11
View file @ 73b66c59
......@@ -123,9 +123,9 @@ ARCHITECTURE str OF node_sdp_filterbank IS
SIGNAL dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL scope_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL selector_en : STD_LOGIC;
SIGNAL subband_calibrated_flag : STD_LOGIC;
SIGNAL i_dp_bsn_source_restart : STD_LOGIC;
SIGNAL selector_en : STD_LOGIC;
SIGNAL subband_calibrated_flag : STD_LOGIC;
SIGNAL dp_bsn_source_restart_pipe : STD_LOGIC;
BEGIN
---------------------------------------------------------------
-- SPECTRAL INVERSION
......@@ -162,18 +162,16 @@ BEGIN
END LOOP;
END PROCESS;
-- pipeline bsn restart signal
u_common_pipeline : ENTITY common_lib.common_pipeline
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
GENERIC MAP (
g_pipeline => c_si_pipeline,
g_in_dat_w => 1,
g_out_dat_w => 1
g_pipeline => c_si_pipeline
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
in_dat(0) => dp_bsn_source_restart,
out_dat(0) => i_dp_bsn_source_restart
in_dat => dp_bsn_source_restart,
out_dat => dp_bsn_source_restart_pipe
);
-- PFB
......@@ -198,7 +196,7 @@ BEGIN
fil_sosi_arr => wpfb_unit_fil_sosi_arr,
out_sosi_arr => wpfb_unit_out_sosi_arr,
dp_bsn_source_restart => i_dp_bsn_source_restart
dp_bsn_source_restart => dp_bsn_source_restart_pipe
);
-- Output PFB streams
......
libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+ 6
− 6
View file @ 73b66c59
......@@ -58,7 +58,7 @@ ENTITY dp_bsn_source_v2 IS
dp_on_pps : IN STD_LOGIC;
dp_on_status : OUT STD_LOGIC;
restart : OUT STD_LOGIC;
bs_restart : OUT STD_LOGIC;
nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
......@@ -103,7 +103,7 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
SIGNAL i_dp_on_status : STD_LOGIC;
SIGNAL nxt_dp_on_status : STD_LOGIC;
SIGNAL nxt_restart : STD_LOGIC;
SIGNAL nxt_bs_restart : STD_LOGIC;
SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
......@@ -134,7 +134,7 @@ BEGIN
nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
nxt_sync <= sync;
nxt_dp_on_status <= i_dp_on_status;
nxt_restart <= '0';
nxt_bs_restart <= '0';
nxt_bsn_time_offset_cnt <= bsn_time_offset_cnt;
nxt_current_bsn_time_offset <= bsn_time_offset;
......@@ -191,7 +191,7 @@ BEGIN
nxt_sync <= '0';
END IF;
IF i_dp_on_status = '0' THEN -- transition from 0 to 1 is a (re)start
nxt_restart <= '1';
nxt_bs_restart <= '1'; -- bs_restart indicates a restart as a pulse on the sop (and sync if dp_on_pps is used).
END IF;
WHEN s_dp_on =>
......@@ -227,7 +227,7 @@ BEGIN
sync <= '0';
block_size_cnt <= (OTHERS=>'0');
i_dp_on_status <= '0';
restart <= '0';
bs_restart <= '0';
bsn_time_offset_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
prev_state <= state;
......@@ -237,7 +237,7 @@ BEGIN
sync <= nxt_sync;
block_size_cnt <= nxt_block_size_cnt;
i_dp_on_status <= nxt_dp_on_status;
restart <= nxt_restart;
bs_restart <= nxt_bs_restart;
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
i_current_bsn_time_offset <= nxt_current_bsn_time_offset;
END IF;
......
libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+ 40
− 17
View file @ 73b66c59
......@@ -25,10 +25,13 @@
-- . A data counter is used to count the valids from the input "val" and compare to g_nof_data_per_block to generate sop/eop.
-- . A block counter is used generate the BSN
-- . The BSN at sync of in_sosi is captured to determine when to generate the sync at the output.
-- . out_sosi.valid is directly connected to val.
-- . IN val is used to indicate when to start outputting the control signals. val is also used for out_sosi.valid, these are connected as wires, so no latency.
-- . IN restart is used to restart the counters. On the restart pulse the in_sosi.bsn is used as the initial value for the bsn counter.
-- Remarks:
-- . The val input signal should be connected to the desired valid of the output. It determines when
-- the first block will start.
-- the first block will start after a (re)start.
-- . It is assumed that the restart pulse is synchornous with in_sosi.sop (if it would have a sop)
-- . IN val should have at least a latency of 1 compared to in_sosi.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
......@@ -49,7 +52,7 @@ ENTITY dp_sync_recover IS
dp_clk : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_rst;
val : IN STD_LOGIC; -- valid at the output
val : IN STD_LOGIC; -- desired valid of the output
restart : IN STD_LOGIC := '0'; -- pulse to restart bsn counter
-- Streaming source
out_sosi : OUT t_dp_sosi
......@@ -60,13 +63,17 @@ END dp_sync_recover;
ARCHITECTURE rtl OF dp_sync_recover IS
TYPE t_reg IS RECORD -- local registers
bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
data_cnt : NATURAL RANGE 0 TO g_nof_data_per_block;
out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
out_sosi : t_dp_sosi;
bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
bsn_before_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
bsn_at_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
restart : STD_LOGIC;
started : STD_LOGIC;
data_cnt : NATURAL RANGE 0 TO g_nof_data_per_block;
out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
out_sosi : t_dp_sosi;
END RECORD;
CONSTANT c_reg_rst : t_reg := ( (OTHERS => '0'), 0, (OTHERS => '0'), c_dp_sosi_rst);
CONSTANT c_reg_rst : t_reg := ( (OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'), '0', '0', 0, (OTHERS => '0'), c_dp_sosi_rst);
-- Define the local registers in t_reg record
SIGNAL r : t_reg;
......@@ -93,31 +100,47 @@ BEGIN
v.out_sosi.valid := val;
v.out_sosi.bsn := r.out_sosi.bsn;
IF restart = '1' THEN -- set initial BSN
v.out_bsn := in_sosi.bsn;
v.data_cnt := c_reg_rst.data_cnt;
IF r.restart = '0' AND restart = '0' THEN -- keep track of last bsn before restart
v.bsn_before_restart := in_sosi.bsn;
END IF;
IF in_sosi.sync = '1' THEN
IF in_sosi.sync = '1' THEN -- capture bsn at sync
v.bsn_at_sync := in_sosi.bsn;
END IF;
IF val = '1' THEN
v.data_cnt := r.data_cnt + 1;
IF r.data_cnt = 0 THEN
IF r.data_cnt = 0 THEN -- generate sop + bsn
v.out_sosi.sop := '1';
v.out_bsn := STD_LOGIC_VECTOR(UNSIGNED(r.out_bsn) + 1);
v.out_bsn := STD_LOGIC_VECTOR(UNSIGNED(r.out_bsn) + 1); -- increase block counter
v.out_sosi.bsn := r.out_bsn;
IF r.out_bsn = r.bsn_at_sync THEN
IF r.out_bsn = r.bsn_at_sync THEN -- generate sync pulse
v.out_sosi.sync := '1';
END IF;
END IF;
IF r.data_cnt = g_nof_data_per_block-1 THEN
IF r.data_cnt = g_nof_data_per_block-1 THEN --reset data counter and generate eop.
v.data_cnt := 0;
v.out_sosi.eop := '1';
END IF;
END IF;
-- overwrite v.out_bsn if a restart has occurd.
IF restart = '1' THEN -- Capture BSN at restart
v.bsn_at_restart := in_sosi.bsn; -- initial bsn value
v.restart := '1';
IF r.started = '0' OR r.out_sosi.bsn = r.bsn_before_restart THEN -- if restarted for the first time or if the restart should happen at the current bsn use the in_sosi.bsn immidiatly.
v.started := '1';
v.restart := '0';
v.out_bsn := in_sosi.bsn;
END IF;
END IF;
-- If the latency is larger than one block, it is needed wait with the restart until the last block has arrived.
IF r.restart = '1' AND r.out_sosi.bsn = r.bsn_before_restart THEN -- set bsn to initial value after restart
v.out_bsn := r.bsn_at_restart;
v.restart := '0';
END IF;
nxt_r <= v;
END PROCESS;
......
libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+ 2
− 2
View file @ 73b66c59
......@@ -52,7 +52,7 @@ ENTITY mms_dp_bsn_source_v2 IS
-- Streaming clock domain
bs_sosi : OUT t_dp_sosi;
restart : OUT STD_LOGIC -- pulse to indicate if the bsn_source has restarted
bs_restart : OUT STD_LOGIC -- pulse to indicate if the bsn_source has restarted
);
END mms_dp_bsn_source_v2;
......@@ -117,7 +117,7 @@ BEGIN
dp_on => dp_on,
dp_on_pps => dp_on_pps,
dp_on_status => dp_on_status,
restart => restart,
bs_restart => bs_restart,
bsn_init => bsn_init,
nof_clk_per_sync => nof_clk_per_sync,
bsn_time_offset => bsn_time_offset,
......
libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+ 31
− 25
View file @ 73b66c59
......@@ -24,7 +24,8 @@
-- Description: The tb verifies:
-- . data valid gaps between blocks
-- . data valid gaps within blocks
-- . output sop, eop, valid, bsn and sync
-- . output sop, eop, valid, bsn and sync
-- . restarts of the dut using IN restart of the dut
-- Usage:
-- > as 8
-- > run -all
......@@ -51,7 +52,8 @@ ENTITY tb_dp_sync_recover IS
g_gap_size_during_block : NATURAL := 0;
g_gap_size_between_block : NATURAL := 0;
g_init_bsn : NATURAL := 23;
g_rep_at_restart : NATURAL := 3;
g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
g_dut_latency : NATURAL := 25;
g_nof_repeat : NATURAL := 14
);
END tb_dp_sync_recover;
......@@ -59,8 +61,6 @@ END tb_dp_sync_recover;
ARCHITECTURE tb OF tb_dp_sync_recover IS
CONSTANT c_dut_latency : NATURAL := 5;
CONSTANT c_dp_clk_period : TIME := 5 ns;
SIGNAL tb_end : STD_LOGIC := '0';
......@@ -73,8 +73,8 @@ ARCHITECTURE tb OF tb_dp_sync_recover IS
SIGNAL restart : STD_LOGIC := '0';
-- Verification
SIGNAL dly_valid_arr : STD_LOGIC_VECTOR(0 TO c_dut_latency) := (OTHERS=>'0');
SIGNAL dly_ref_sosi_arr : t_dp_sosi_arr(0 TO c_dut_latency) := (OTHERS => c_dp_sosi_rst);
SIGNAL dly_valid_arr : STD_LOGIC_VECTOR(0 TO g_dut_latency) := (OTHERS=>'0');
SIGNAL dly_ref_sosi_arr : t_dp_sosi_arr(0 TO g_dut_latency) := (OTHERS => c_dp_sosi_rst);
SIGNAL exp_sync : STD_LOGIC := '0';
SIGNAL out_hold_sop : STD_LOGIC := '0';
SIGNAL exp_size : NATURAL := g_nof_data_per_block;
......@@ -90,6 +90,7 @@ BEGIN
------------------------------------------------------------------------------
p_stimuli : PROCESS
VARIABLE v_bsn : NATURAL;
BEGIN
proc_common_wait_until_low(dp_clk, rst);
proc_common_wait_some_cycles(dp_clk, 5);
......@@ -99,14 +100,14 @@ BEGIN
ref_sosi.sync <= '1';
ref_sosi.sop <= '1';
ref_sosi.valid <= '1';
IF I = 0 OR I = g_rep_at_restart THEN
ref_sosi.bsn <= TO_DP_BSN(g_init_bsn);
v_bsn := g_init_bsn + I * g_nof_blk_per_sync;
IF v_bsn = g_bsn_at_restart OR I = 0 THEN
v_bsn := g_init_bsn;
restart <= '1';
ELSIF I > g_rep_at_restart THEN
ref_sosi.bsn <= TO_DP_BSN(g_init_bsn + (I - g_rep_at_restart) * g_nof_blk_per_sync);
ELSE
ref_sosi.bsn <= TO_DP_BSN(g_init_bsn + I * g_nof_blk_per_sync);
ELSIF v_bsn > g_bsn_at_restart THEN
v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync - g_bsn_at_restart;
END IF;
ref_sosi.bsn <= TO_DP_BSN(v_bsn);
proc_common_wait_some_cycles(dp_clk, 1);
ref_sosi.sync <= '0';
ref_sosi.sop <= '0';
......@@ -128,16 +129,21 @@ BEGIN
-- Generate next blocks after sync
FOR J IN 0 TO g_nof_blk_per_sync-2 LOOP
v_bsn := g_init_bsn + I * g_nof_blk_per_sync + J + 1;
ref_sosi.sop <= '1';
ref_sosi.valid <= '1';
IF I >= g_rep_at_restart THEN
ref_sosi.bsn <= TO_DP_BSN(g_init_bsn + (I - g_rep_at_restart) * g_nof_blk_per_sync + J + 1);
ELSE
ref_sosi.bsn <= TO_DP_BSN(g_init_bsn + I * g_nof_blk_per_sync + J + 1);
IF v_bsn = g_bsn_at_restart THEN
v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync + J + 1 - g_bsn_at_restart;
restart <= '1';
ELSIF v_bsn > g_bsn_at_restart THEN
v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync + J + 1 - g_bsn_at_restart;
END IF;
ref_sosi.bsn <= TO_DP_BSN(v_bsn);
proc_common_wait_some_cycles(dp_clk, 1);
ref_sosi.sync <= '0';
ref_sosi.sop <= '0';
restart <= '0';
-- Optionally apply valid='0' during block of data
ref_sosi.valid <= '0';
......@@ -178,7 +184,7 @@ BEGIN
-- Streaming sink
in_sosi => ref_sosi,
val => dly_ref_sosi_arr(c_dut_latency).valid,
val => dly_ref_sosi_arr(g_dut_latency).valid,
restart => restart,
-- Streaming source
out_sosi => out_sosi
......@@ -190,15 +196,15 @@ BEGIN
-- . use some general Verification means from tb_dp_pkg.vhd, dp_stream_verify.vhd
------------------------------------------------------------------------------
dly_ref_sosi_arr(0) <= ref_sosi;
dly_ref_sosi_arr(1 TO c_dut_latency) <= dly_ref_sosi_arr(0 TO c_dut_latency-1) WHEN rising_edge(dp_clk);
dly_ref_sosi_arr(1 TO g_dut_latency) <= dly_ref_sosi_arr(0 TO g_dut_latency-1) WHEN rising_edge(dp_clk);
p_exp_sync : PROCESS(dp_clk)
VARIABLE blk_cnt : NATURAL := 0;
BEGIN
IF rising_edge(dp_clk) THEN
exp_sync <= '0';
IF dly_ref_sosi_arr(c_dut_latency-1).sop = '1' THEN
IF dly_ref_sosi_arr(c_dut_latency-1).sync = '1' OR blk_cnt >= g_nof_blk_per_sync-1 THEN
IF dly_ref_sosi_arr(g_dut_latency-1).sop = '1' THEN
IF dly_ref_sosi_arr(g_dut_latency-1).sync = '1' OR blk_cnt >= g_nof_blk_per_sync-1 THEN
blk_cnt := 0;
exp_sync <= '1';
ELSE
......@@ -211,11 +217,11 @@ BEGIN
p_verify_out_sosi : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
ASSERT out_sosi.valid = dly_ref_sosi_arr(c_dut_latency).valid REPORT "Wrong out_sosi.valid" SEVERITY ERROR;
ASSERT out_sosi.sop = dly_ref_sosi_arr(c_dut_latency).sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
ASSERT out_sosi.eop = dly_ref_sosi_arr(c_dut_latency).eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
ASSERT out_sosi.bsn = dly_ref_sosi_arr(c_dut_latency).bsn REPORT "Wrong out_sosi.bsn" SEVERITY ERROR;
ASSERT out_sosi.sync = dly_ref_sosi_arr(c_dut_latency).sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
ASSERT out_sosi.valid = dly_ref_sosi_arr(g_dut_latency).valid REPORT "Wrong out_sosi.valid" SEVERITY ERROR;
ASSERT out_sosi.sop = dly_ref_sosi_arr(g_dut_latency).sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
ASSERT out_sosi.eop = dly_ref_sosi_arr(g_dut_latency).eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
ASSERT out_sosi.bsn = dly_ref_sosi_arr(g_dut_latency).bsn REPORT "Wrong out_sosi.bsn" SEVERITY ERROR;
ASSERT out_sosi.sync = dly_ref_sosi_arr(g_dut_latency).sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
END IF;
END PROCESS;
......
libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
+ 9
− 3
View file @ 73b66c59
......@@ -42,10 +42,16 @@ BEGIN
-- g_gap_size_during_block : NATURAL := 0;
-- g_gap_size_between_block : NATURAL := 0;
-- g_init_bsn : NATURAL := 23;
-- g_rep_at_restart : NATURAL := 3;
-- g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
-- g_dut_latency : NATURAL := 25;
-- g_nof_repeat : NATURAL := 14
u_no_gaps : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 32, 0, 0, 8, 3, 14);
u_gap : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 32, 1, 3, 8, 3, 14);
u_no_gaps : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 0, 0, 3, 50, 10, 14);
u_gap : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 10, 14);
u_restart_at_sync : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 10, 14);
u_restart_at_sync_hi : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 100, 14);
u_restart_at_sync_lo : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 1, 14);
u_high_latency : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 100, 14);
u_low_latency : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 1, 14);
END tb;
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