added tb for dp_sync_recover and added restart signal to bsn_source_v2

that is used by dp_sync_recover

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd

@@ -394,6 +394,8 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   SIGNAL pfb_sosi_arr                      : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);         
   SIGNAL fsub_sosi_arr                     : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);        
   
+  SIGNAL dp_bsn_source_restart             : STD_LOGIC;
+ 
   SIGNAL bf_udp_sosi_arr                   : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);         
   SIGNAL bf_udp_siso_arr                   : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);    
   SIGNAL bf_10GbE_hdr_fields_out_arr       : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
@@ -792,7 +794,8 @@ BEGIN
     jesd204b_sync_n            => JESD204B_SYNC_N,   
  
     -- Streaming data output
-    out_sosi_arr               => ait_sosi_arr        
+    out_sosi_arr               => ait_sosi_arr,
+    dp_bsn_source_restart      => dp_bsn_source_restart        
   );
 
   -----------------------------------------------------------------------------
@@ -812,6 +815,7 @@ BEGIN
       in_sosi_arr           => ait_sosi_arr,    
       pfb_sosi_arr          => pfb_sosi_arr,
       fsub_sosi_arr         => fsub_sosi_arr,
+      dp_bsn_source_restart => dp_bsn_source_restart,
 
       sst_udp_sosi          => udp_tx_sosi_arr(0),
       sst_udp_siso          => udp_tx_siso_arr(0),

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -99,7 +99,8 @@ ENTITY node_sdp_adc_input_and_timing IS
     jesd204b_sync_n                : OUT   STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
 
     -- Streaming data output
-    out_sosi_arr                   : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0)        
+    out_sosi_arr                   : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);        
+    dp_bsn_source_restart          : OUT STD_LOGIC
 
   );
 END node_sdp_adc_input_and_timing;
@@ -123,6 +124,9 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
   SIGNAL rx_rst                     : STD_LOGIC; 
   SIGNAL rx_sysref                  : STD_LOGIC; 
 
+  SIGNAL arst                       : STD_LOGIC;
+  SIGNAL i_dp_bsn_source_restart    : STD_LOGIC;
+
   -- Sosis and sosi arrays
   SIGNAL rx_sosi_arr                : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);         
   SIGNAL dp_shiftram_snk_in_arr     : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);         
@@ -252,7 +256,9 @@ BEGIN
     reg_miso          => reg_bsn_source_v2_miso,
     
     -- Streaming clock domain
-    bs_sosi           => bs_sosi
+    bs_sosi           => bs_sosi,
+
+    restart           => i_dp_bsn_source_restart
   );
 
   u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
@@ -463,6 +469,24 @@ BEGIN
       );
   END GENERATE;
 
+  -- use common dc fifo for restart signal
+  u_common_fifo_dc_restart : ENTITY common_lib.common_fifo_dc
+  GENERIC MAP (
+    g_dat_w     => 1,
+    g_nof_words => c_dp_fifo_dc_size
+  )
+  PORT MAP (
+    rst     => arst,
+    wr_clk  => rx_clk,
+    wr_dat(0)  => i_dp_bsn_source_restart,
+    wr_req  => bs_sosi.valid,
+    rd_clk  => dp_clk,
+    rd_dat(0)  => dp_bsn_source_restart,
+    rd_req  => '1'
+  );
+
+  arst <= rx_rst OR dp_rst;
+
   -----------------------------------------------------------------------------
   -- JESD Control register
   -----------------------------------------------------------------------------

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd

@@ -63,6 +63,8 @@ ENTITY node_sdp_filterbank IS
     sst_udp_sosi  : OUT t_dp_sosi;
     sst_udp_siso  : IN  t_dp_siso := c_dp_siso_rst;
 
+    dp_bsn_source_restart : IN STD_LOGIC;
+
     mm_rst             : IN  STD_LOGIC;
     mm_clk             : IN  STD_LOGIC;
 
@@ -99,6 +101,8 @@ ARCHITECTURE str OF node_sdp_filterbank IS
 
   CONSTANT c_nof_masters : POSITIVE := 2;
 
+  CONSTANT c_si_pipeline : NATURAL := 1;
+
   SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
   SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
 
@@ -121,6 +125,7 @@ ARCHITECTURE str OF node_sdp_filterbank IS
   
   SIGNAL selector_en             : STD_LOGIC;
   SIGNAL subband_calibrated_flag : STD_LOGIC;
+  SIGNAL i_dp_bsn_source_restart : STD_LOGIC;
 BEGIN
   ---------------------------------------------------------------
   -- SPECTRAL INVERSION 
@@ -128,7 +133,7 @@ BEGIN
   u_si_arr : ENTITY si_lib.si_arr
   GENERIC MAP (
     g_nof_streams => c_sdp_S_pn, 
-    g_pipeline    => 1,  
+    g_pipeline    => c_si_pipeline,  
     g_dat_w       => c_sdp_W_adc 
   )
   PORT MAP(
@@ -157,6 +162,20 @@ BEGIN
     END LOOP;
   END PROCESS;
 
+  -- pipeline bsn restart signal
+  u_common_pipeline : ENTITY common_lib.common_pipeline
+  GENERIC MAP (
+    g_pipeline  => c_si_pipeline,
+    g_in_dat_w  => 1,
+    g_out_dat_w => 1
+  )
+  PORT MAP (
+    rst        => dp_rst,
+    clk        => dp_clk,
+    in_dat(0)  => dp_bsn_source_restart,
+    out_dat(0) => i_dp_bsn_source_restart
+  ); 
+
   -- PFB 
   u_wpfb_unit_dev : ENTITY wpfb_lib.wpfb_unit_dev
   GENERIC MAP (
@@ -177,7 +196,9 @@ BEGIN
 
     in_sosi_arr        => wpfb_unit_in_sosi_arr, 
     fil_sosi_arr       => wpfb_unit_fil_sosi_arr, 
-    out_sosi_arr       => wpfb_unit_out_sosi_arr 
+    out_sosi_arr       => wpfb_unit_out_sosi_arr,
+ 
+    dp_bsn_source_restart => i_dp_bsn_source_restart
   );
   
   -- Output PFB streams

libraries/base/dp/hdllib.cfg

@@ -256,6 +256,7 @@ test_bench_files =
     tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
     tb/vhdl/tb_dp_sync_insert.vhd
     tb/vhdl/tb_dp_sync_insert_v2.vhd
+    tb/vhdl/tb_dp_sync_recover.vhd
     tb/vhdl/tb_dp_folder.vhd
     tb/vhdl/tb_dp_switch.vhd
     tb/vhdl/tb_dp_counter_func.vhd
@@ -308,6 +309,7 @@ test_bench_files =
     tb/vhdl/tb_tb_dp_sync_checker.vhd
     tb/vhdl/tb_tb_dp_sync_insert.vhd
     tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+    tb/vhdl/tb_tb_dp_sync_recover.vhd
     tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
     tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
     tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
@@ -370,6 +372,7 @@ regression_test_vhdl =
     tb/vhdl/tb_mms_dp_sync_checker.vhd
     tb/vhdl/tb_tb_dp_sync_insert.vhd
     tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+    tb/vhdl/tb_tb_dp_sync_recover.vhd
     tb/vhdl/tb_dp_counter_func.vhd
     tb/vhdl/tb_tb_dp_counter.vhd
     tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd

libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd

@@ -58,6 +58,7 @@ ENTITY dp_bsn_source_v2 IS
     dp_on_pps               : IN  STD_LOGIC;
 
     dp_on_status            : OUT STD_LOGIC;
+    restart                 : OUT STD_LOGIC;
  
     nof_clk_per_sync        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
     bsn_init                : IN  STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
@@ -102,6 +103,7 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
  
   SIGNAL i_dp_on_status     : STD_LOGIC;
   SIGNAL nxt_dp_on_status   : STD_LOGIC;
+  SIGNAL nxt_restart        : STD_LOGIC;
 
   SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
   SIGNAL bsn_time_offset_cnt     : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
@@ -132,6 +134,7 @@ BEGIN
     nxt_clk_cnt                 <= INCR_UVEC(clk_cnt, 1);
     nxt_sync                    <= sync;
     nxt_dp_on_status            <= i_dp_on_status;
+    nxt_restart                 <= '0';
     nxt_bsn_time_offset_cnt     <= bsn_time_offset_cnt;
     nxt_current_bsn_time_offset <= bsn_time_offset;
 
@@ -187,6 +190,9 @@ BEGIN
           nxt_src_out.sync <= '1';
           nxt_sync <= '0';
         END IF;
+        IF i_dp_on_status = '0' THEN -- transition from 0 to 1 is a (re)start
+          nxt_restart <= '1';
+        END IF;
 
       WHEN s_dp_on =>
         nxt_src_out.valid  <= '1';
@@ -221,6 +227,7 @@ BEGIN
       sync           <= '0'; 
       block_size_cnt <= (OTHERS=>'0');
       i_dp_on_status <= '0';
+      restart        <= '0';
       bsn_time_offset_cnt <= (OTHERS=>'0');
     ELSIF rising_edge(clk) THEN
       prev_state     <= state;
@@ -230,6 +237,7 @@ BEGIN
       sync           <= nxt_sync;
       block_size_cnt <= nxt_block_size_cnt;
       i_dp_on_status <= nxt_dp_on_status;
+      restart        <= nxt_restart;
       bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
       i_current_bsn_time_offset <= nxt_current_bsn_time_offset;
     END IF;

libraries/base/dp/src/vhdl/dp_sync_recover.vhd

@@ -29,7 +29,6 @@
 -- Remarks:
 --  . The val input signal should be connected to the desired valid of the output. It determines when 
 --    the first block will start.
---  . g_initial_bsn can be used to start with a non-zero bsn
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib;
@@ -41,7 +40,6 @@ USE work.dp_stream_pkg.ALL;
 
 ENTITY dp_sync_recover IS
   GENERIC (
-    g_initial_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0) := (OTHERS => '0');
     g_nof_data_per_block : POSITIVE := 1
   );
   PORT (    
@@ -52,6 +50,7 @@ ENTITY dp_sync_recover IS
     
     in_sosi    : IN  t_dp_sosi := c_dp_sosi_rst;
     val        : IN  STD_LOGIC; -- valid at the output
+    restart    : IN  STD_LOGIC := '0'; -- pulse to restart bsn counter
     -- Streaming source
     out_sosi   : OUT t_dp_sosi
   );
@@ -67,7 +66,7 @@ ARCHITECTURE rtl OF dp_sync_recover IS
     out_sosi    : t_dp_sosi;
   END RECORD;
 
-  CONSTANT c_reg_rst  : t_reg := ( (OTHERS => '0'), 0, g_initial_bsn, c_dp_sosi_rst);  
+  CONSTANT c_reg_rst  : t_reg := ( (OTHERS => '0'), 0, (OTHERS => '0'), c_dp_sosi_rst);  
 
   -- Define the local registers in t_reg record
   SIGNAL r         : t_reg;
@@ -94,9 +93,15 @@ BEGIN
     v.out_sosi.valid := val;
     v.out_sosi.bsn   := r.out_sosi.bsn;
 
+    IF restart = '1' THEN -- set initial BSN
+      v.out_bsn  := in_sosi.bsn;
+      v.data_cnt := c_reg_rst.data_cnt;
+    END IF;
+
     IF in_sosi.sync = '1' THEN
       v.bsn_at_sync  := in_sosi.bsn; 
     END IF;
+
     IF val = '1' THEN
       v.data_cnt := r.data_cnt + 1;
       IF r.data_cnt = 0 THEN
@@ -111,10 +116,6 @@ BEGIN
         v.data_cnt := 0;
         v.out_sosi.eop := '1';
       END IF;
-    ELSE
-      v.out_sosi := c_reg_rst.out_sosi;
-      v.out_bsn  := c_reg_rst.out_bsn;
-      v.data_cnt := c_reg_rst.data_cnt;
     END IF;
  
     nxt_r <= v;

libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd

@@ -50,7 +50,9 @@ ENTITY mms_dp_bsn_source_v2 IS
     reg_miso          : OUT t_mem_miso;  -- actual ranges defined by c_mm_reg
     
     -- Streaming clock domain
-    bs_sosi           : OUT t_dp_sosi
+    bs_sosi           : OUT t_dp_sosi;
+
+    restart           : OUT STD_LOGIC  -- pulse to indicate if the bsn_source has restarted
   );
 END mms_dp_bsn_source_v2;
 
@@ -115,6 +117,7 @@ BEGIN
     dp_on                   => dp_on,
     dp_on_pps               => dp_on_pps,
     dp_on_status            => dp_on_status,
+    restart                 => restart,
     bsn_init                => bsn_init,
     nof_clk_per_sync        => nof_clk_per_sync,
     bsn_time_offset         => bsn_time_offset,

libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify dp_sync_recover
+-- Description: The tb verifies:
+--  . data valid gaps between blocks
+--  . data valid gaps within blocks
+--  . output sop, eop, valid, bsn and sync 
+-- Usage:
+-- > as 8
+-- > run -all
+--
+-- * The tb is self stopping because tb_end will stop the simulation by
+--   stopping the clk and thus all toggling.
+-------------------------------------------------------------------------------
+  
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+
+ENTITY tb_dp_sync_recover IS
+  GENERIC (
+    g_nof_data_per_block     : NATURAL := 16; 
+    g_nof_blk_per_sync       : NATURAL := 8;
+    g_gap_size_during_block  : NATURAL := 0;
+    g_gap_size_between_block : NATURAL := 0;
+    g_init_bsn               : NATURAL := 23;
+    g_rep_at_restart         : NATURAL := 3;
+    g_nof_repeat             : NATURAL := 14
+  );
+END tb_dp_sync_recover;
+
+
+ARCHITECTURE tb OF tb_dp_sync_recover IS
+
+  CONSTANT c_dut_latency         : NATURAL := 5;
+  
+  CONSTANT c_dp_clk_period       : TIME := 5 ns;
+
+  SIGNAL tb_end                    : STD_LOGIC := '0';
+  SIGNAL dp_clk                    : STD_LOGIC := '1';
+  SIGNAL rst                       : STD_LOGIC := '1';
+    
+  -- DUT
+  SIGNAL ref_sosi                  : t_dp_sosi := c_dp_sosi_rst;
+  SIGNAL out_sosi                  : t_dp_sosi;
+  SIGNAL restart                   : STD_LOGIC := '0';
+
+  -- Verification
+  SIGNAL dly_valid_arr             : STD_LOGIC_VECTOR(0 TO c_dut_latency) := (OTHERS=>'0');
+  SIGNAL dly_ref_sosi_arr          : t_dp_sosi_arr(0 TO c_dut_latency) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL exp_sync                  : STD_LOGIC := '0';
+  SIGNAL out_hold_sop              : STD_LOGIC := '0';
+  SIGNAL exp_size                  : NATURAL := g_nof_data_per_block;
+  SIGNAL cnt_size                  : NATURAL;
+  
+BEGIN
+
+  dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
+  rst <= '1', '0' AFTER c_dp_clk_period*7;
+
+  ------------------------------------------------------------------------------
+  -- STIMULI
+  ------------------------------------------------------------------------------
+  
+  p_stimuli : PROCESS
+  BEGIN
+    proc_common_wait_until_low(dp_clk, rst);
+    proc_common_wait_some_cycles(dp_clk, 5);
+
+    FOR I IN 0 TO g_nof_repeat-1 LOOP
+      -- Generate first block with sync
+      ref_sosi.sync  <= '1';
+      ref_sosi.sop   <= '1';
+      ref_sosi.valid <= '1';
+      IF I = 0 OR I = g_rep_at_restart THEN
+        ref_sosi.bsn   <= TO_DP_BSN(g_init_bsn);
+        restart <= '1';
+      ELSIF I > g_rep_at_restart THEN
+        ref_sosi.bsn   <= TO_DP_BSN(g_init_bsn + (I - g_rep_at_restart) * g_nof_blk_per_sync);
+      ELSE
+        ref_sosi.bsn   <= TO_DP_BSN(g_init_bsn + I * g_nof_blk_per_sync);
+      END IF;
+      proc_common_wait_some_cycles(dp_clk, 1);
+      ref_sosi.sync  <= '0';
+      ref_sosi.sop   <= '0';
+      restart        <= '0'; 
+      
+      -- Optionally apply valid='0' during block of data
+      ref_sosi.valid <= '0';
+      proc_common_wait_some_cycles(dp_clk, g_gap_size_during_block);
+      ref_sosi.valid <= '1';
+      
+      proc_common_wait_some_cycles(dp_clk, g_nof_data_per_block-2);
+      ref_sosi.eop   <= '1';
+      proc_common_wait_some_cycles(dp_clk, 1);
+      ref_sosi.eop   <= '0';
+      ref_sosi.valid <= '0';
+
+      -- Optionally apply valid='0' between block of data
+      proc_common_wait_some_cycles(dp_clk, g_gap_size_between_block);
+      
+      -- Generate next blocks after sync
+      FOR J IN 0 TO g_nof_blk_per_sync-2 LOOP
+        ref_sosi.sop   <= '1';
+        ref_sosi.valid <= '1';
+        IF I >= g_rep_at_restart THEN
+          ref_sosi.bsn   <= TO_DP_BSN(g_init_bsn + (I - g_rep_at_restart) * g_nof_blk_per_sync + J + 1);
+        ELSE
+          ref_sosi.bsn   <= TO_DP_BSN(g_init_bsn + I * g_nof_blk_per_sync + J + 1);
+        END IF;
+        proc_common_wait_some_cycles(dp_clk, 1);
+        ref_sosi.sync  <= '0';
+        ref_sosi.sop   <= '0';
+
+        -- Optionally apply valid='0' during block of data
+        ref_sosi.valid <= '0';
+        proc_common_wait_some_cycles(dp_clk, g_gap_size_during_block);
+        ref_sosi.valid <= '1';
+
+        proc_common_wait_some_cycles(dp_clk, g_nof_data_per_block-2);
+        ref_sosi.eop   <= '1';
+        proc_common_wait_some_cycles(dp_clk, 1);
+        ref_sosi.eop   <= '0';
+        ref_sosi.valid <= '0';
+        
+        -- Optionally apply valid='0' between block of data
+        proc_common_wait_some_cycles(dp_clk, g_gap_size_between_block);
+      END LOOP;
+    END LOOP; 
+    
+    -- End of stimuli
+    proc_common_wait_some_cycles(dp_clk, 100);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+  
+  ref_sosi.data  <= INCR_UVEC(ref_sosi.data, 1) WHEN rising_edge(dp_clk);
+  ref_sosi.re    <= INCR_UVEC(ref_sosi.re,   2) WHEN rising_edge(dp_clk);
+  ref_sosi.im    <= INCR_UVEC(ref_sosi.im,   3) WHEN rising_edge(dp_clk);
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_dut: ENTITY work.dp_sync_recover
+  GENERIC MAP (
+    g_nof_data_per_block => g_nof_data_per_block
+  )
+  PORT MAP (
+    dp_rst        => rst,
+    dp_clk        => dp_clk,
+
+    -- Streaming sink
+    in_sosi       => ref_sosi,
+    val           => dly_ref_sosi_arr(c_dut_latency).valid,
+    restart       => restart,
+    -- Streaming source
+    out_sosi      => out_sosi
+  );
+  
+  ------------------------------------------------------------------------------
+  -- Verification
+  -- . use some DUT specific verification
+  -- . use some general Verification means from tb_dp_pkg.vhd, dp_stream_verify.vhd
+  ------------------------------------------------------------------------------
+  dly_ref_sosi_arr(0)                  <= ref_sosi;
+  dly_ref_sosi_arr(1 TO c_dut_latency) <= dly_ref_sosi_arr(0 TO c_dut_latency-1) WHEN rising_edge(dp_clk);
+
+  p_exp_sync : PROCESS(dp_clk)
+    VARIABLE blk_cnt : NATURAL := 0;
+  BEGIN
+    IF rising_edge(dp_clk) THEN
+      exp_sync <= '0'; 
+      IF dly_ref_sosi_arr(c_dut_latency-1).sop = '1' THEN
+        IF dly_ref_sosi_arr(c_dut_latency-1).sync = '1' OR blk_cnt >= g_nof_blk_per_sync-1 THEN
+          blk_cnt := 0;
+          exp_sync <= '1';
+        ELSE
+          blk_cnt := blk_cnt+1;
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  p_verify_out_sosi : PROCESS(dp_clk)
+  BEGIN
+    IF rising_edge(dp_clk) THEN
+      ASSERT out_sosi.valid = dly_ref_sosi_arr(c_dut_latency).valid REPORT "Wrong out_sosi.valid" SEVERITY ERROR;
+      ASSERT out_sosi.sop   = dly_ref_sosi_arr(c_dut_latency).sop   REPORT "Wrong out_sosi.sop"   SEVERITY ERROR;
+      ASSERT out_sosi.eop   = dly_ref_sosi_arr(c_dut_latency).eop   REPORT "Wrong out_sosi.eop"   SEVERITY ERROR;
+      ASSERT out_sosi.bsn   = dly_ref_sosi_arr(c_dut_latency).bsn   REPORT "Wrong out_sosi.bsn"   SEVERITY ERROR;
+      ASSERT out_sosi.sync  = dly_ref_sosi_arr(c_dut_latency).sync  REPORT "Wrong out_sosi.sync"  SEVERITY ERROR;
+    END IF;
+  END PROCESS;
+  
+  -- Verify output packet ctrl
+  proc_dp_verify_sop_and_eop(dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_hold_sop);
+  -- Verify output packet block size
+  proc_dp_verify_block_size(exp_size, dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, cnt_size);
+  
+
+      
+END tb;

libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify multiple variations of tb_dp_sync_recover
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_dp_sync_recover IS
+END tb_tb_dp_sync_recover;
+
+ARCHITECTURE tb OF tb_tb_dp_sync_recover IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+--    g_nof_data_per_block     : NATURAL := 16; 
+--    g_nof_blk_per_sync       : NATURAL := 8;
+--    g_gap_size_during_block  : NATURAL := 0;
+--    g_gap_size_between_block : NATURAL := 0;
+--    g_init_bsn               : NATURAL := 23;
+--    g_rep_at_restart         : NATURAL := 3;
+--    g_nof_repeat             : NATURAL := 14
+
+  u_no_gaps            : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 32, 0, 0, 8, 3, 14);
+  u_gap                : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 32, 1, 3, 8, 3, 14);
+  
+END tb;

libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd

@@ -382,7 +382,8 @@ entity wpfb_unit_dev is
     ram_bg_data_miso      : out t_mem_miso;
     in_sosi_arr           : in  t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
     fil_sosi_arr          : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
-    out_sosi_arr       : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0)
+    out_sosi_arr          : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+    dp_bsn_source_restart : in  std_logic
   );
 end entity wpfb_unit_dev;
 
@@ -455,6 +456,7 @@ architecture str of wpfb_unit_dev is
   
   type reg_type is record
     in_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+    bsn_source_restart : STD_LOGIC;
   end record;
 
   signal r, rin : reg_type;
@@ -467,6 +469,7 @@ begin
   begin
     v                    := r;
     v.in_sosi_arr        := in_sosi_arr;
+    v.bsn_source_restart := dp_bsn_source_restart;
     rin                  <= v;
   end process comb;
 
@@ -635,7 +638,7 @@ begin
 
       in_sosi  => fft_out_sosi,
       val      => fft_out_sosi.valid,
-
+      restart  => r.bsn_source_restart,
       out_sosi => ctrl_pfb_out_sosi
     );