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Commit 70cdb4b8 authored by Eric Kooistra's avatar Eric Kooistra
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Added xgmii_link_status.

parent 273103ae
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......@@ -115,6 +115,7 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- 10G MAC XGMII interface
SIGNAL xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
SIGNAL xgmii_tx_data : STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
SIGNAL xgmii_rx_data : STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
......@@ -249,6 +250,11 @@ BEGIN
END IF;
END PROCESS;
no_dut : IF c_st_loopback=TRUE GENERATE
rx_sosi <= tx_sosi;
tx_siso <= rx_siso;
END GENERATE;
gen_dut : IF c_st_loopback=FALSE GENERATE
dut : ENTITY work.tech_mac_10g
GENERIC MAP (
......@@ -277,16 +283,12 @@ BEGIN
rx_src_in => rx_siso,
-- XGMII
xgmii_link_status => xgmii_link_status,
xgmii_tx_data => xgmii_tx_data, -- 72 bit
xgmii_rx_data => xgmii_rx_data -- 72 bit
);
END GENERATE;
no_dut : IF c_st_loopback=TRUE GENERATE
rx_sosi <= tx_sosi;
tx_siso <= rx_siso;
END GENERATE;
-- Loopback XGMII
xgmii_rx_data <= TRANSPORT xgmii_tx_data AFTER phy_delay;
......
......@@ -93,6 +93,7 @@ ENTITY tech_mac_10g IS
rx_src_in : IN t_dp_siso;
-- XGMII
xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
);
......@@ -134,7 +135,7 @@ BEGIN
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
xgmii_tx_data, xgmii_rx_data);
xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
......@@ -142,7 +143,7 @@ BEGIN
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
rx_clk_312, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
xgmii_tx_data, xgmii_rx_data);
xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
......
......@@ -54,6 +54,7 @@ ENTITY tech_mac_10g_arria10 IS
rx_src_in : IN t_dp_siso;
-- XGMII
xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
);
......@@ -135,7 +136,7 @@ BEGIN
avalon_st_rxstatus_data => OPEN,
avalon_st_rxstatus_error => OPEN,
link_fault_status_xgmii_rx_data => OPEN,
link_fault_status_xgmii_rx_data => xgmii_link_status, -- 0=ok, 1=local fault, 2=remote fault
unidirectional_en => OPEN,
unidirectional_remote_fault_dis => OPEN
......
......@@ -32,6 +32,10 @@ PACKAGE tech_mac_10g_component_pkg IS
FUNCTION func_tech_mac_10g_csr_addr_w(c_technology : NATURAL) RETURN NATURAL;
CONSTANT c_tech_mac_10g_link_status_w : NATURAL := 2;
TYPE t_tech_mac_10g_xgmii_status_arr IS ARRAY(INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);
CONSTANT c_tech_mac_10g_data_w : NATURAL := c_xgmii_data_w; -- = 64
CONSTANT c_tech_mac_10g_symbol_w : NATURAL := c_byte_w; -- = 8 bit
......
......@@ -52,6 +52,7 @@ ENTITY tech_mac_10g_stratixiv IS
rx_src_in : IN t_dp_siso;
-- XGMII
xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
);
......@@ -121,7 +122,7 @@ BEGIN
avalon_st_rxstatus_data => OPEN,
avalon_st_rxstatus_error => OPEN,
link_fault_status_xgmii_rx_data => OPEN
link_fault_status_xgmii_rx_data => xgmii_link_status -- 0=ok, 1=local fault, 2=remote fault
);
END str;
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