diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
index ef1dcdca81f10e9c040c510383665b22d20112b0..43f1a6ee17b11be49a0792c0485a13c78d415e42 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
@@ -115,6 +115,7 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- 10G MAC XGMII interface
+ SIGNAL xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
SIGNAL xgmii_tx_data : STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
SIGNAL xgmii_rx_data : STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
@@ -249,6 +250,11 @@ BEGIN
END IF;
END PROCESS;
+ no_dut : IF c_st_loopback=TRUE GENERATE
+ rx_sosi <= tx_sosi;
+ tx_siso <= rx_siso;
+ END GENERATE;
+
gen_dut : IF c_st_loopback=FALSE GENERATE
dut : ENTITY work.tech_mac_10g
GENERIC MAP (
@@ -258,35 +264,31 @@ BEGIN
)
PORT MAP (
-- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- csr_mosi => mm_mosi, -- CSR = control status register
- csr_miso => mm_miso,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ csr_mosi => mm_mosi, -- CSR = control status register
+ csr_miso => mm_miso,
-- ST
- tx_clk_312 => tx_ref_clk_312,
- tx_clk_156 => tx_ref_clk_156, -- 156.25 MHz local reference
- tx_rst => tx_rst,
- tx_snk_in => tx_sosi, -- 64 bit data
- tx_snk_out => tx_siso,
+ tx_clk_312 => tx_ref_clk_312,
+ tx_clk_156 => tx_ref_clk_156, -- 156.25 MHz local reference
+ tx_rst => tx_rst,
+ tx_snk_in => tx_sosi, -- 64 bit data
+ tx_snk_out => tx_siso,
- rx_clk_312 => rx_phy_clk_312,
- rx_clk_156 => rx_phy_clk_156, -- 156.25 MHz from rx phy
- rx_rst => rx_rst,
- rx_src_out => rx_sosi, -- 64 bit data
- rx_src_in => rx_siso,
+ rx_clk_312 => rx_phy_clk_312,
+ rx_clk_156 => rx_phy_clk_156, -- 156.25 MHz from rx phy
+ rx_rst => rx_rst,
+ rx_src_out => rx_sosi, -- 64 bit data
+ rx_src_in => rx_siso,
-- XGMII
- xgmii_tx_data => xgmii_tx_data, -- 72 bit
- xgmii_rx_data => xgmii_rx_data -- 72 bit
+ xgmii_link_status => xgmii_link_status,
+ xgmii_tx_data => xgmii_tx_data, -- 72 bit
+ xgmii_rx_data => xgmii_rx_data -- 72 bit
);
END GENERATE;
- no_dut : IF c_st_loopback=TRUE GENERATE
- rx_sosi <= tx_sosi;
- tx_siso <= rx_siso;
- END GENERATE;
-
-- Loopback XGMII
xgmii_rx_data <= TRANSPORT xgmii_tx_data AFTER phy_delay;
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 5fe23c99e97e8146575382b45599ef415900ff2f..5e2370274f34669c2b07d7e52f474e9028107fcc 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -74,27 +74,28 @@ ENTITY tech_mac_10g IS
);
PORT (
-- MM
- mm_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- csr_mosi : IN t_mem_mosi; -- CSR = control status register
- csr_miso : OUT t_mem_miso;
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ csr_mosi : IN t_mem_mosi; -- CSR = control status register
+ csr_miso : OUT t_mem_miso;
-- ST
- tx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
- tx_clk_156 : IN STD_LOGIC; -- 156.25 MHz local reference
- tx_rst : IN STD_LOGIC;
- tx_snk_in : IN t_dp_sosi; -- 64 bit data
- tx_snk_out : OUT t_dp_siso;
+ tx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
+ tx_clk_156 : IN STD_LOGIC; -- 156.25 MHz local reference
+ tx_rst : IN STD_LOGIC;
+ tx_snk_in : IN t_dp_sosi; -- 64 bit data
+ tx_snk_out : OUT t_dp_siso;
- rx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
- rx_clk_156 : IN STD_LOGIC; -- 156.25 MHz from rx phy
- rx_rst : IN STD_LOGIC;
- rx_src_out : OUT t_dp_sosi; -- 64 bit data
- rx_src_in : IN t_dp_siso;
+ rx_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz
+ rx_clk_156 : IN STD_LOGIC; -- 156.25 MHz from rx phy
+ rx_rst : IN STD_LOGIC;
+ rx_src_out : OUT t_dp_sosi; -- 64 bit data
+ rx_src_in : IN t_dp_siso;
-- XGMII
- xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
- xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
+ xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
+ xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
);
END tech_mac_10g;
@@ -134,7 +135,7 @@ BEGIN
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
- xgmii_tx_data, xgmii_rx_data);
+ xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
@@ -142,7 +143,7 @@ BEGIN
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
rx_clk_312, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
- xgmii_tx_data, xgmii_rx_data);
+ xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
index 229731dba55b47210d7e4ed34150997268db6159..4539cfd73055c63835bedae12c9ed68a245d338f 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
@@ -35,27 +35,28 @@ USE work.tech_mac_10g_component_pkg.ALL;
ENTITY tech_mac_10g_arria10 IS
PORT (
-- MM
- mm_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- csr_mosi : IN t_mem_mosi; -- CSR = control status register
- csr_miso : OUT t_mem_miso;
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ csr_mosi : IN t_mem_mosi; -- CSR = control status register
+ csr_miso : OUT t_mem_miso;
-- ST
- tx_clk_312 : IN STD_LOGIC;
- tx_clk_156 : IN STD_LOGIC;
- tx_rst : IN STD_LOGIC;
- tx_snk_in : IN t_dp_sosi;
- tx_snk_out : OUT t_dp_siso;
+ tx_clk_312 : IN STD_LOGIC;
+ tx_clk_156 : IN STD_LOGIC;
+ tx_rst : IN STD_LOGIC;
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
- rx_clk_312 : IN STD_LOGIC;
- rx_clk_156 : IN STD_LOGIC;
- rx_rst : IN STD_LOGIC;
- rx_src_out : OUT t_dp_sosi;
- rx_src_in : IN t_dp_siso;
+ rx_clk_312 : IN STD_LOGIC;
+ rx_clk_156 : IN STD_LOGIC;
+ rx_rst : IN STD_LOGIC;
+ rx_src_out : OUT t_dp_sosi;
+ rx_src_in : IN t_dp_siso;
-- XGMII
- xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
- xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
+ xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
+ xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
);
END tech_mac_10g_arria10;
@@ -135,7 +136,7 @@ BEGIN
avalon_st_rxstatus_data => OPEN,
avalon_st_rxstatus_error => OPEN,
- link_fault_status_xgmii_rx_data => OPEN,
+ link_fault_status_xgmii_rx_data => xgmii_link_status, -- 0=ok, 1=local fault, 2=remote fault
unidirectional_en => OPEN,
unidirectional_remote_fault_dis => OPEN
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 598f8ce6a0861db48a2e94339240d65561229302..a3c31889b101bed51b1e18c59061c90f1d5a7c65 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -32,6 +32,10 @@ PACKAGE tech_mac_10g_component_pkg IS
FUNCTION func_tech_mac_10g_csr_addr_w(c_technology : NATURAL) RETURN NATURAL;
+ CONSTANT c_tech_mac_10g_link_status_w : NATURAL := 2;
+
+ TYPE t_tech_mac_10g_xgmii_status_arr IS ARRAY(INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);
+
CONSTANT c_tech_mac_10g_data_w : NATURAL := c_xgmii_data_w; -- = 64
CONSTANT c_tech_mac_10g_symbol_w : NATURAL := c_byte_w; -- = 8 bit
diff --git a/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd b/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd
index b087325a7b99301b00211c63ce21a1b48c67662d..ea4e4d48ddafed21483796416898fd91e7f3b8b0 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd
@@ -33,28 +33,29 @@ USE technology_lib.technology_pkg.ALL;
USE work.tech_mac_10g_component_pkg.ALL;
ENTITY tech_mac_10g_stratixiv IS
- PORT (
- -- MM
- mm_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- csr_mosi : IN t_mem_mosi; -- CSR = control status register
- csr_miso : OUT t_mem_miso;
+ PORT (
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ csr_mosi : IN t_mem_mosi; -- CSR = control status register
+ csr_miso : OUT t_mem_miso;
-- ST
- tx_clk : IN STD_LOGIC;
- tx_rst : IN STD_LOGIC;
- tx_snk_in : IN t_dp_sosi;
- tx_snk_out : OUT t_dp_siso;
-
- rx_clk : IN STD_LOGIC;
- rx_rst : IN STD_LOGIC;
- rx_src_out : OUT t_dp_sosi;
- rx_src_in : IN t_dp_siso;
-
+ tx_clk : IN STD_LOGIC;
+ tx_rst : IN STD_LOGIC;
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+
+ rx_clk : IN STD_LOGIC;
+ rx_rst : IN STD_LOGIC;
+ rx_src_out : OUT t_dp_sosi;
+ rx_src_in : IN t_dp_siso;
+
-- XGMII
- xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
- xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
- );
+ xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
+ xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
+ );
END tech_mac_10g_stratixiv;
@@ -75,53 +76,53 @@ BEGIN
tx_snk_out.xon <= '1';
u_ip_mac_10g : ip_stratixiv_mac_10g
- PORT MAP (
- csr_clk_clk => mm_clk,
- csr_reset_reset_n => mm_rst_n,
-
- csr_address => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0), -- 13 bit
- csr_read => csr_mosi.rd,
- csr_write => csr_mosi.wr,
- csr_writedata => csr_mosi.wrdata(c_word_w-1 DOWNTO 0), -- 32 bit
- csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit
- csr_waitrequest => csr_miso.waitrequest,
-
- tx_clk_clk => tx_clk,
- tx_reset_reset_n => tx_rst_n,
-
- avalon_st_tx_ready => tx_snk_out.ready,
- avalon_st_tx_startofpacket => tx_snk_in.sop,
- avalon_st_tx_endofpacket => tx_snk_in.eop,
- avalon_st_tx_valid => tx_snk_in.valid,
- avalon_st_tx_data => tx_snk_in.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
- avalon_st_tx_empty => tx_snk_in.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
- avalon_st_tx_error => tx_snk_in.err(c_tech_mac_10g_tx_error_w-1 DOWNTO 0), -- 1 bit
- avalon_st_pause_data => (OTHERS=>'0'),
-
- xgmii_tx_data => xgmii_tx_data, -- 72 bit
-
- avalon_st_txstatus_valid => OPEN,
- avalon_st_txstatus_data => OPEN,
- avalon_st_txstatus_error => OPEN,
-
- rx_clk_clk => rx_clk,
- rx_reset_reset_n => rx_rst_n,
-
- xgmii_rx_data => xgmii_rx_data, -- 72 bit
-
- avalon_st_rx_ready => rx_src_in.ready,
- avalon_st_rx_startofpacket => rx_src_out.sop,
- avalon_st_rx_endofpacket => rx_src_out.eop,
- avalon_st_rx_valid => rx_src_out.valid,
- avalon_st_rx_data => rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
- avalon_st_rx_empty => rx_src_out.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
- avalon_st_rx_error => rx_src_out.err(c_tech_mac_10g_rx_error_w-1 DOWNTO 0), -- 6 bit
-
- avalon_st_rxstatus_valid => OPEN,
- avalon_st_rxstatus_data => OPEN,
- avalon_st_rxstatus_error => OPEN,
-
- link_fault_status_xgmii_rx_data => OPEN
- );
+ PORT MAP (
+ csr_clk_clk => mm_clk,
+ csr_reset_reset_n => mm_rst_n,
+
+ csr_address => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0), -- 13 bit
+ csr_read => csr_mosi.rd,
+ csr_write => csr_mosi.wr,
+ csr_writedata => csr_mosi.wrdata(c_word_w-1 DOWNTO 0), -- 32 bit
+ csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit
+ csr_waitrequest => csr_miso.waitrequest,
+
+ tx_clk_clk => tx_clk,
+ tx_reset_reset_n => tx_rst_n,
+
+ avalon_st_tx_ready => tx_snk_out.ready,
+ avalon_st_tx_startofpacket => tx_snk_in.sop,
+ avalon_st_tx_endofpacket => tx_snk_in.eop,
+ avalon_st_tx_valid => tx_snk_in.valid,
+ avalon_st_tx_data => tx_snk_in.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
+ avalon_st_tx_empty => tx_snk_in.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
+ avalon_st_tx_error => tx_snk_in.err(c_tech_mac_10g_tx_error_w-1 DOWNTO 0), -- 1 bit
+ avalon_st_pause_data => (OTHERS=>'0'),
+
+ xgmii_tx_data => xgmii_tx_data, -- 72 bit
+
+ avalon_st_txstatus_valid => OPEN,
+ avalon_st_txstatus_data => OPEN,
+ avalon_st_txstatus_error => OPEN,
+
+ rx_clk_clk => rx_clk,
+ rx_reset_reset_n => rx_rst_n,
+
+ xgmii_rx_data => xgmii_rx_data, -- 72 bit
+
+ avalon_st_rx_ready => rx_src_in.ready,
+ avalon_st_rx_startofpacket => rx_src_out.sop,
+ avalon_st_rx_endofpacket => rx_src_out.eop,
+ avalon_st_rx_valid => rx_src_out.valid,
+ avalon_st_rx_data => rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
+ avalon_st_rx_empty => rx_src_out.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
+ avalon_st_rx_error => rx_src_out.err(c_tech_mac_10g_rx_error_w-1 DOWNTO 0), -- 6 bit
+
+ avalon_st_rxstatus_valid => OPEN,
+ avalon_st_rxstatus_data => OPEN,
+ avalon_st_rxstatus_error => OPEN,
+
+ link_fault_status_xgmii_rx_data => xgmii_link_status -- 0=ok, 1=local fault, 2=remote fault
+ );
END str;