work in process

applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Create address by counting input valids
+--
+-- Description:
+--  The counter starts on the first valid = '1' clockcylce, the counter stops 
+--  when valid = '0'.
+--
+-- Remark:
+--  Use VHDL coding template from:
+--  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+--  The maximum value of the address is determend by g_tech_ddr.
+
+
+LIBRARY IEEE, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY pack IS
+  GENERIC (
+
+    g_nof_streams	: POSITIVE := 12;
+    g_data_w		  : NATURAL  := 14
+
+  );
+  PORT (
+
+    clk	      	  : IN  STD_LOGIC;
+    in_sosi_arr   : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    out_data 	    : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
+
+  );
+END pack;
+
+ARCHITECTURE rtl OF pack IS
+
+BEGIN
+
+  gen_extract_and_pack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    out_data(g_data_w*(I+1)-1 DOWNTO g_data_w*I) <= in_sosi_arr(I).data(g_data_w-1 DOWNTO 0);
+  END GENERATE;
+
+END rtl;