work in process

applications/lofar2/libraries/ddrctrl/hdllib.cfg

@@ -6,9 +6,11 @@ hdl_lib_technology =
 
 synth_files = 
     src/vhdl/address_counter.vhd 
+    src/vhdl/pack.vhd
 
 test_bench_files =
     tb/vhdl/tb_address_counter.vhd
+    tb/vhdl/tb_pack.vhd
 
 regression_test_vhdl = 
 

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd

---------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 --
--- Copyright (C) 2022
+-- Copyright 2022
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
---------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Self checking and self-stopping tb for pack.vhd
+-- Usage:
+-- > run -a
 
 LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -47,10 +49,12 @@ ARCHITECTURE tb OF tb_pack IS
 
   CONSTANT  c_data_w          : NATURAL         := g_nof_streams * g_data_w; -- 168
 
+  CONSTANT  c_testv           : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := "111111111111111111111111110011111111110000111111110000001111110000000011110000000000110000000000000000000000000000000000000011000000000011110000000011111100000011111111";
+                                                                          
+
   SIGNAL    tb_end            : STD_LOGIC       := '0';
 
   SIGNAL    clk               : STD_LOGIC       := '1';
-
   SIGNAL    in_sosi_arr       : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init);
 
   SIGNAL    out_data          : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
@@ -59,6 +63,10 @@ BEGIN
 
   clk               <= NOT clk OR tb_end AFTER c_clk_period/2;
 
+  check_data : FOR I IN 0 TO g_nof_streams - 1 GENERATE
+    ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) REPORT "Data does not match" SEVERITY ERROR;
+  END GENERATE;
+
   p_mm : PROCESS
   BEGIN
 
@@ -67,23 +75,16 @@ BEGIN
     WAIT UNTIL rising_edge(clk);  -- align to rising edge
     WAIT FOR c_clk_period*2;
 
-    in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0)    <= "11111111111111";
-    in_sosi_arr(1).data(g_data_w - 1 DOWNTO 0)    <= "11111111111100";
-    in_sosi_arr(2).data(g_data_w - 1 DOWNTO 0)    <= "11111111110000";
-    in_sosi_arr(3).data(g_data_w - 1 DOWNTO 0)    <= "11111111000000";
-    in_sosi_arr(4).data(g_data_w - 1 DOWNTO 0)    <= "11111100000000";
-    in_sosi_arr(5).data(g_data_w - 1 DOWNTO 0)    <= "11110000000000";
-    in_sosi_arr(6).data(g_data_w - 1 DOWNTO 0)    <= "11000000000000";
-    in_sosi_arr(7).data(g_data_w - 1 DOWNTO 0)    <= "00000000000000";
-    in_sosi_arr(8).data(g_data_w - 1 DOWNTO 0)    <= "00000000000011";
-    in_sosi_arr(9).data(g_data_w - 1 DOWNTO 0)    <= "00000000001111";
-    in_sosi_arr(10).data(g_data_w - 1 DOWNTO 0)   <= "00000000111111";
-    in_sosi_arr(11).data(g_data_w - 1 DOWNTO 0)   <= "00000011111111";
-
-    for_loop : FOR J IN 0 TO 4 LOOP
+    fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
+      in_sosi_arr(I).data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I)   <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
+    END LOOP;
+
+
+    change_in_sosi_arr : FOR J IN 0 TO 4 LOOP
       WAIT FOR c_clk_period*1;
-      gen_switch_data : FOR I IN 0 TO g_nof_streams-1 LOOP
-        in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0)    <= NOT in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0);
+      in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0)    <= in_sosi_arr(g_nof_streams-1).data(g_data_w - 1 DOWNTO 0);
+      gen_switch_data : FOR I IN 1 TO g_nof_streams-1 LOOP
+        in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0)    <= in_sosi_arr(I-1).data(g_data_w - 1 DOWNTO 0);
        END LOOP;
     END LOOP;