Skip to content
Snippets Groups Projects
Commit 70a06f7e authored by Pieter Donker's avatar Pieter Donker
Browse files

add ip files and changed code to get minimal wroking design

parent 8a684eb0
No related branches found
No related tags found
No related merge requests found
Expand all Hide whitespace changes
Inline Side-by-side
Showing
with 13452 additions and 3 deletions
applications/arts/designs/arts_unb2b_sc3/hdllib.cfg
+ 4
− 3
View file @ 70a06f7e
...@@ -25,12 +25,13 @@ hdl_lib_include_ip = ...@@ -25,12 +25,13 @@ hdl_lib_include_ip =
synth_files = synth_files =
src/vhdl/qsys_arts_unb2b_sc3_pkg.vhd src/vhdl/qsys_arts_unb2b_sc3_pkg.vhd
src/vhdl/arts_unb2b_sc3_mm_master.vhd src/vhdl/arts_unb2b_sc3_mm_master.vhd
src/vhdl/arts_unb2b_sc3_input.vhd # src/vhdl/arts_unb2b_sc3_input.vhd
src/vhdl/arts_unb2b_sc3_processing.vhd # src/vhdl/arts_unb2b_sc3_processing.vhd
src/vhdl/arts_unb2b_sc3_output.vhd # src/vhdl/arts_unb2b_sc3_output.vhd
src/vhdl/arts_unb2b_sc3.vhd src/vhdl/arts_unb2b_sc3.vhd
test_bench_files = test_bench_files =
tb/vhdl/tb_arts_unb2b_sc3.vhd
[modelsim_project_file] [modelsim_project_file]
......
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0/qsys_arts_unb2b_sc3_avs_eth_0_generation.rpt 0 → 100644
+ 67
− 0
View file @ 70a06f7e
Info: Generated by version: 17.0.2 build 297
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0 --family="Arria 10" --part=10AX115U2F45E1SG
Warning: qsys_arts_unb2b_sc3_avs_eth_0: Component type avs2_eth_coe is not in the library
Error: qsys_arts_unb2b_sc3_avs_eth_0.qsys_arts_unb2b_sc3_avs_eth_0: Component avs2_eth_coe 1.0 not found or could not be instantiated
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0 --family="Arria 10" --part=10AX115U2F45E1SG
Warning: qsys_arts_unb2b_sc3_avs_eth_0: Component type avs2_eth_coe is not in the library
Error: qsys_arts_unb2b_sc3_avs_eth_0.qsys_arts_unb2b_sc3_avs_eth_0: Component avs2_eth_coe 1.0 not found or could not be instantiated
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
Info: Finished: Create HDL design files for synthesis
Info: Starting: Generate IP Core documentation.
Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_avs_eth_0. No files generated.
Info: Finished: Generate IP Core documentation.
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1/qsys_arts_unb2b_sc3_avs_eth_1_generation.rpt 0 → 100644
+ 67
− 0
View file @ 70a06f7e
Info: Generated by version: 17.0.2 build 297
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1 --family="Arria 10" --part=10AX115U2F45E1SG
Warning: qsys_arts_unb2b_sc3_avs_eth_1: Component type avs2_eth_coe is not in the library
Error: qsys_arts_unb2b_sc3_avs_eth_1.qsys_arts_unb2b_sc3_avs_eth_1: Component avs2_eth_coe 1.0 not found or could not be instantiated
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1 --family="Arria 10" --part=10AX115U2F45E1SG
Warning: qsys_arts_unb2b_sc3_avs_eth_1: Component type avs2_eth_coe is not in the library
Error: qsys_arts_unb2b_sc3_avs_eth_1.qsys_arts_unb2b_sc3_avs_eth_1: Component avs2_eth_coe 1.0 not found or could not be instantiated
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
Info: Finished: Create HDL design files for synthesis
Info: Starting: Generate IP Core documentation.
Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_avs_eth_1. No files generated.
Info: Finished: Generate IP Core documentation.
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.bsf 0 → 100644
+ 82
− 0
View file @ 70a06f7e
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 144)
(text "qsys_arts_unb2b_sc3_clk_1" (rect 44 -1 160 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "in_clk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
(text "in_clk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 80 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8)))
(text "reset_n" (rect 4 101 46 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 80 112)(line_width 1))
)
(port
(pt 256 72)
(output)
(text "clk_out" (rect 0 0 28 12)(font "Arial" (font_size 8)))
(text "clk_out" (rect 219 61 261 72)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 176 72)(line_width 1))
)
(port
(pt 256 112)
(output)
(text "reset_n_out" (rect 0 0 48 12)(font "Arial" (font_size 8)))
(text "reset_n_out" (rect 194 101 260 112)(font "Arial" (font_size 8)))
(line (pt 256 112)(pt 176 112)(line_width 1))
)
(drawing
(text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 161 67 340 144)(font "Arial" (color 0 0 0)))
(text "clk_in" (rect 47 43 130 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0)))
(text "clk_in_reset" (rect 9 83 90 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0)))
(text "clk_reset" (rect 177 83 408 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 140 107 322 224)(font "Arial" (color 0 0 0)))
(text " qsys_arts_unb2b_sc3_clk_1 " (rect 129 128 420 266)(font "Arial" ))
(line (pt 80 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 128)(line_width 1))
(line (pt 80 128)(pt 176 128)(line_width 1))
(line (pt 80 32)(pt 80 128)(line_width 1))
(line (pt 175 52)(pt 175 76)(line_width 1))
(line (pt 174 52)(pt 174 76)(line_width 1))
(line (pt 81 52)(pt 81 76)(line_width 1))
(line (pt 82 52)(pt 82 76)(line_width 1))
(line (pt 81 92)(pt 81 116)(line_width 1))
(line (pt 82 92)(pt 82 116)(line_width 1))
(line (pt 175 92)(pt 175 116)(line_width 1))
(line (pt 174 92)(pt 174 116)(line_width 1))
(line (pt 0 0)(pt 256 0)(line_width 1))
(line (pt 256 0)(pt 256 144)(line_width 1))
(line (pt 0 144)(pt 256 144)(line_width 1))
(line (pt 0 0)(pt 0 144)(line_width 1))
)
)
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.cmp 0 → 100644
+ 9
− 0
View file @ 70a06f7e
component qsys_arts_unb2b_sc3_clk_1 is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_n_out : out std_logic -- reset_n
);
end component qsys_arts_unb2b_sc3_clk_1;
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.html 0 → 100644
+ 153
− 0
View file @ 70a06f7e
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for qsys_arts_unb2b_sc3_clk_1</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">qsys_arts_unb2b_sc3_clk_1</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2018.05.30.14:37:26</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk_0&#160;</td>
<td class="main" rowspan="2">qsys_arts_unb2b_sc3_clk_1</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/></span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
</table>
<a name="module_clk_0"> </a>
<div>
<hr/>
<h2>clk_0</h2>clock_source v17.0
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">125000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.01 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
</tr>
</table>
</body>
</html>
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qgsynthc 0 → 100644
+ 57
− 0
View file @ 70a06f7e
<?xml version="1.0" ?>
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
<instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_clk_1</instanceKey>
<instanceData xsi:type="data">
<parameters></parameters>
<interconnectAssignments>
<interconnectAssignment>
<name>qsys_mm.clockCrossingAdapter</name>
<value>HANDSHAKE</value>
</interconnectAssignment>
<interconnectAssignment>
<name>qsys_mm.maxAdditionalLatency</name>
<value>0</value>
</interconnectAssignment>
</interconnectAssignments>
<className>qsys_arts_unb2b_sc3_clk_1</className>
<version>1.0</version>
<name>qsys_arts_unb2b_sc3_clk_1</name>
<uniqueName>qsys_arts_unb2b_sc3_clk_1</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">clk_0</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>clockFrequency</name>
<value>125000000</value>
</parameter>
<parameter>
<name>clockFrequencyKnown</name>
<value>true</value>
</parameter>
<parameter>
<name>inputClockFrequency</name>
<value>0</value>
</parameter>
<parameter>
<name>resetSynchronousEdges</name>
<value>NONE</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>clock_source</className>
<version>17.0</version>
<name>clk_0</name>
<uniqueName>qsys_arts_unb2b_sc3_clk_1_clock_source_170_yubjnyi</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
<path>qsys_arts_unb2b_sc3_clk_1.clk_0</path>
</instanceData>
<children></children>
</node>
</children>
</node>
\ No newline at end of file
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qip 0 → 100644
+ 25
− 0
View file @ 70a06f7e
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TOOL_VERSION "17.0.2"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_clk_1.sopcinfo"]
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_clk_1 HAS_SOPCINFO 1 GENERATION_ID 1527683845"
set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_clk_1.cmp"]
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_clk_1.ip"]
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19jbGtfMQ=="
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzg0NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfSU5fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfSU5fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfSU5fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_clk_1.vhd"]
applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_bb.v 0 → 100644
+ 12
− 0
View file @ 70a06f7e
module qsys_arts_unb2b_sc3_clk_1 (
clk_out,
in_clk,
reset_n,
reset_n_out);
output clk_out;
input in_clk;
input reset_n;
output reset_n_out;
endmodule
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment