add ip files and changed code to get minimal wroking design

...s_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.vhd

..._arts_unb2b_sc3_cpu_0/synth/qsys_arts_unb2b_sc3_cpu_0.vhd

...ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0.ip

...b2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v

...unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.bsf

...unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.cmp

...nb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.html

..._sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qgsynthc

...unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qip

...2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.regmap

..._sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.sopcinfo

...unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.xml

...nb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_bb.v

...tag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_generation.rpt

...2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.v

..._sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.vhd

...sc3_jtag_uart_0/synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd

...ys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip

...chip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v

...onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex