add ip files and changed code to get minimal wroking design

...qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v

...ts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc

...arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v

...0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v

...pu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v

..._altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v

...a_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif

...sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif

...sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif

...sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v

...3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.bsf

...3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.cmp

.../qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.html

...s_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qgsynthc

...3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qip

...s_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.sopcinfo

...3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.xml

.../qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_bb.v

..._unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_generation.rpt

...sys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.v