corrected compile_ip.tcl files

libraries/technology/ddr/hdllib.cfg

@@ -19,6 +19,8 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
                   ip_arria10_e1sg_ddr4_4g_2000
                   ip_arria10_e1sg_ddr4_8g_2400
                   ip_arria10_e2sg_ddr4_8g_1600
+                  ip_arria10_e2sg_ddr4_16g_1600_64b
+                  ip_arria10_e2sg_ddr4_16g_1600_72b
 #                 ip_arria10_e2sg_ddr4_8g_2400
 hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
                    ip_arria10_ddr4_mem_model_141
@@ -44,6 +46,8 @@ hdl_lib_disclose_library_clause_names =
     ip_stratixiv_ddr3_mem_model                      ip_stratixiv_ddr3_mem_model_lib
     ip_arria10_ddr4_mem_model_141                    ip_arria10_ddr4_mem_model_141
     ip_arria10_e2sg_ddr4_8g_1600                     ip_arria10_e2sg_ddr4_8g_1600_altera_emif_191
+    ip_arria10_e2sg_ddr4_16g_1600_64b                ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910
+    ip_arria10_e2sg_ddr4_16g_1600_72b                ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910
 #   ip_arria10_e2sg_ddr4_8g_2400                     ip_arria10_e2sg_ddr4_8g_2400_altera_emif_191
     
 synth_files =

libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd

@@ -257,7 +257,7 @@ BEGIN
   
   gen_ip_arria10_e2sg_ddr4_16g_1600_72b : IF g_tech_ddr.name="DDR4" AND c_gigabytes=16 AND g_tech_ddr.mts=1600 AND g_tech_ddr.dq_w=72 GENERATE
 
-    u_ip_arria10_e2sg_ddr4_8g_1600_72b : ip_arria10_e2sg_ddr4_8g_1600_72b
+    u_ip_arria10_e2sg_ddr4_16g_1600_72b : ip_arria10_e2sg_ddr4_16g_1600_72b
     PORT MAP (
       amm_ready_0         => ctlr_miso.waitrequest_n,                                   --     ctrl_amm_avalon_slave_0.waitrequest_n
       amm_read_0          => ctlr_mosi.rd,                                              --                            .read

libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl

@@ -36,3 +36,11 @@ vmap  alt_mem_if_jtag_master_191            ./work/
 
   vcom         "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_8g_1600_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191           
 
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom         "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191           
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom         "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191           
+  

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl

@@ -33,3 +33,12 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 vmap  altera_avalon_mm_bridge_191         ./work/                       
 
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
+
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
+  

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl

@@ -33,5 +33,13 @@ vmap  altera_avalon_onchip_memory2_1920    ./work/
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
+  
 # copy previous 'set' and 'vcom' lines to include more ddr4 variants
                                                       

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl

@@ -34,7 +34,15 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 
 vmap  altera_avalon_sc_fifo_191  ./work/
   vlog      "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_sc_fifo_191_e5eqkcq.v"  -work altera_avalon_sc_fifo_191
-   
+
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog      "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_sc_fifo_191_e5eqkcq.v"  -work altera_avalon_sc_fifo_191
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vlog      "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_sc_fifo_191_e5eqkcq.v"  -work altera_avalon_sc_fifo_191
+    
                       
 
                                                       

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl

@@ -41,10 +41,9 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 # ddr4_16g_1600_72b
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
 
-  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_slbjghy_top.sv"           -work altera_emif_arch_nf_191
-  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_slbjghy_io_aux.sv"        -work altera_emif_arch_nf_191
-  vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_slbjghy.vhd"              -work altera_emif_arch_nf_191
-
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv"           -work altera_emif_arch_nf_191
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv"        -work altera_emif_arch_nf_191
+  vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd"              -work altera_emif_arch_nf_191
 # ddr4_8g_1600
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
@@ -105,24 +104,62 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
 
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_3yb4cia.vhd"          -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_3yb4cia.vhd"          -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
+
 
 vmap  altera_avalon_onchip_memory2_1920    ./work/
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
+
+
 
 vmap  altera_avalon_mm_bridge_191         ./work/
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
 
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
+
+
 vmap  altera_emif_cal_slave_nf_191        ./work/
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
 
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
+
+
 
 vmap  altera_emif_1910                     ./work/
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910_jhcj6zy.vhd"                                  -work altera_emif_1910
 
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910_rvperma.vhd"                             -work altera_emif_1910
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_3t6zvqq.vhd"                             -work altera_emif_1910
+

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl

@@ -40,9 +40,9 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 # ddr4_16g_1600_72b
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
 
-  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_slbjghy_top.sv"           -work altera_emif_arch_nf_191
-  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_slbjghy_io_aux.sv"        -work altera_emif_arch_nf_191
-  vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_slbjghy.vhd"              -work altera_emif_arch_nf_191
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv"           -work altera_emif_arch_nf_191
+  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv"        -work altera_emif_arch_nf_191
+  vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd"              -work altera_emif_arch_nf_191
 
 # ddr4_8g_1600
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl

@@ -35,3 +35,12 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 vmap  altera_ip_col_if_191 ./work/
                                               
   vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
+
+# ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
+

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl

@@ -33,3 +33,11 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 vmap  altera_merlin_master_translator_191 ./work/
         
   vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191
+
+# ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl

@@ -35,3 +35,10 @@ vmap  altera_merlin_slave_translator_191  ./work/
                                                       
   vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
 
+# ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl

@@ -35,4 +35,14 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191
 
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191 
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
+  vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191

libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl

@@ -37,4 +37,13 @@ vmap  channel_adapter_191                   ./work/
   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_191_cco4x3a.sv"    -work channel_adapter_191                  
   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_191_uc27kqq.sv"    -work channel_adapter_191              
 
-                                                      
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_channel_adapter_191_cco4x3a.sv"    -work channel_adapter_191                  
+  vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_channel_adapter_191_uc27kqq.sv"    -work channel_adapter_191              
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_channel_adapter_191_cco4x3a.sv"    -work channel_adapter_191                   
+   vlog -sv  "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_channel_adapter_191_uc27kqq.sv"    -work channel_adapter_191                                                                       
+ 

libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl

@@ -36,4 +36,12 @@ vmap  timing_adapter_191   ./work/
                   
   vlog -sv  "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_timing_adapter_191_rrgemwi.sv"  -work timing_adapter_191                   
 
+#ddr4_16g_1600_64b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+  vlog -sv  "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_timing_adapter_191_rrgemwi.sv"  -work timing_adapter_191                   
+
+# ddr4_16g_1600_72b
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+  vlog -sv  "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_timing_adapter_191_rrgemwi.sv"  -work timing_adapter_191                   
+  
                                                       

libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_ddr4_16g_1600_64b
-hdl_library_clause_name = ip_arria10_e2sg_ddr4_16g_1600_64bit_altera_emif_1910
+hdl_library_clause_name = ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_emif_1910 ip_arria10_e2sg_altera_merlin_master_translator_191