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Commit 2cbcd0e6 authored by Reinier van der Walle's avatar Reinier van der Walle
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disabled regtest

parent e368ebeb
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Pipeline #39493 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/libraries/ddrctrl/hdllib.cfg
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...@@ -16,7 +16,7 @@ synth_files = ...@@ -16,7 +16,7 @@ synth_files =
src/vhdl/ddrctrl.vhd src/vhdl/ddrctrl.vhd
test_bench_files = test_bench_files =
tb/vhdl/tb_ddrctrl.vhd #tb/vhdl/tb_ddrctrl.vhd
regression_test_vhdl = regression_test_vhdl =
......
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