Missing hdl_lib_uses_synth in hdllib file, and typos in vhdl

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -72,8 +72,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
   CONSTANT c_jesd204b_mm_addr_w            : NATURAL :=8;
   CONSTANT c_jesd204b_rx_data_w            : NATURAL :=32;
   CONSTANT c_jesd204b_rx_framer_data_w     : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
-  CONSTANT c_jesd204b_rx_somf_w            : NATURAL :=c_jesd204b_rx_somf_w/8; -- One somf bit per octet
-  CONSTANT c_jesd204b_rx_framer_somf_w     : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+  CONSTANT c_jesd204b_rx_somf_w            : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
+  CONSTANT c_jesd204b_rx_framer_somf_w     : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
 
   -- JESD204 control status registers
   SIGNAL jesd204b_mosi_arr          : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
@@ -165,7 +165,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       rxlink_rst_n_reset_n              : in  std_logic                     := 'X';             -- reset_n
       rxphy_clk                  : out std_logic_vector(0 downto 0);                     -- export
       sof                        : out std_logic_vector(3 downto 0);                     -- export
-      somf                       : out std_logic_vector(c_jesd204b_rx_somf_w downto 0);                     -- export
+      somf                       : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0);                     -- export
       sysref                     : in  std_logic                     := 'X'              -- export
     );
   end component ip_arria10_e1sg_jesd204b_rx;
@@ -261,7 +261,7 @@ BEGIN
         dev_lane_aligned           => dev_lane_aligned_arr(i),           
         dev_sync_n                 => jesd204b_sync_n_arr(i),
         jesd204_rx_avs_chipselect         => '0', --jesd204b_mosi_arr(i).chipselect,
-        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w downto 0),
+        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
         jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
         jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
         jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,

libraries/technology/jesd204b/hdllib.cfg

 hdl_lib_name = tech_jesd204b
 hdl_library_clause_name = tech_jesd204b_lib
-hdl_lib_uses_synth = technology common dp
+hdl_lib_uses_synth = technology common dp ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b
 hdl_lib_uses_ip = ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b
 hdl_lib_uses_sim = 
 #hdl_lib_technology = ip_arria10_e1sg ip_arria10_e2sg