remove g_sim_level, use constants for data path widths

applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl

@@ -20,4 +20,4 @@
 ###############################################################################
 
 source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd

@@ -443,7 +443,6 @@ BEGIN
   u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
   GENERIC MAP(
     g_sim                => g_sim,                
-    g_sim_level          => 1,          
     g_nof_channels       => c_nof_streams_jesd204b    
   )
   PORT MAP(

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -39,7 +39,6 @@ USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
 ENTITY ip_arria10_e1sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
@@ -69,6 +68,13 @@ END ip_arria10_e1sg_jesd204b;
 
 ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
 
+  -- JESD IP constants
+  CONSTANT c_jesd204b_mm_addr_w            : NATURAL :=8;
+  CONSTANT c_jesd204b_rx_data_w            : NATURAL :=32;
+  CONSTANT c_jesd204b_rx_framer_data_w     : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+  CONSTANT c_jesd204b_rx_somf_w            : NATURAL :=c_jesd204b_rx_somf_w/8; -- One somf bit per octet
+  CONSTANT c_jesd204b_rx_framer_somf_w     : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+
   -- JESD204 control status registers
   SIGNAL jesd204b_mosi_arr          : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
   SIGNAL jesd204b_miso_arr          : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 
@@ -105,9 +111,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
   SIGNAL jesd204b_sysref_2          : STD_LOGIC;               
 
   -- Data path
-  SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(32*g_nof_channels-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_channels-1 DOWNTO 0);               
   SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL jesd204b_rx_somf_arr       : STD_LOGIC_VECTOR(4*g_nof_channels-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_somf_arr       : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_channels-1 DOWNTO 0);               
 
 
   -- Component declarations for the IP blocks
@@ -131,7 +137,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       dev_lane_aligned           : out std_logic;                                        -- export
       dev_sync_n                 : out std_logic;                                        -- export
       jesd204_rx_avs_chipselect  : in  std_logic                     := 'X';             -- chipselect
-      jesd204_rx_avs_address     : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- address
+      jesd204_rx_avs_address     : in  std_logic_vector(c_jesd204b_mm_addr_w-1 downto 0)  := (others => 'X'); -- address
       jesd204_rx_avs_read        : in  std_logic                     := 'X';             -- read
       jesd204_rx_avs_readdata    : out std_logic_vector(31 downto 0);                    -- readdata
       jesd204_rx_avs_waitrequest : out std_logic;                                        -- waitrequest
@@ -145,11 +151,11 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       jesd204_rx_dlb_errdetect   : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
       jesd204_rx_dlb_kchar_data  : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
       jesd204_rx_frame_error     : in  std_logic                     := 'X';             -- export
-      jesd204_rx_int                : out std_logic;                                        -- irq
-      jesd204_rx_link_data              : out std_logic_vector(31 downto 0);                    -- data
-      jesd204_rx_link_valid             : out std_logic;                                        -- valid
-      jesd204_rx_link_ready             : in  std_logic                     := 'X';             -- ready
-      pll_ref_clk                   : in  std_logic                     := 'X';             -- clk
+      jesd204_rx_int             : out std_logic;                                        -- irq
+      jesd204_rx_link_data       : out std_logic_vector(c_jesd204b_rx_data_w-1 downto 0);                    -- data
+      jesd204_rx_link_valid      : out std_logic;                                        -- valid
+      jesd204_rx_link_ready      : in  std_logic                     := 'X';             -- ready
+      pll_ref_clk                : in  std_logic                     := 'X';             -- clk
       rx_analogreset             : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_analogreset
       rx_cal_busy                : out std_logic_vector(0 downto 0);                     -- rx_cal_busy
       rx_digitalreset            : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_digitalreset
@@ -159,7 +165,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       rxlink_rst_n_reset_n              : in  std_logic                     := 'X';             -- reset_n
       rxphy_clk                  : out std_logic_vector(0 downto 0);                     -- export
       sof                        : out std_logic_vector(3 downto 0);                     -- export
-      somf                       : out std_logic_vector(3 downto 0);                     -- export
+      somf                       : out std_logic_vector(c_jesd204b_rx_somf_w downto 0);                     -- export
       sysref                     : in  std_logic                     := 'X'              -- export
     );
   end component ip_arria10_e1sg_jesd204b_rx;
@@ -217,10 +223,13 @@ BEGIN
 
   jesd204b_frame_clk <= rxframe_clk;
 
+  -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug 
+  -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse
   gen_simclock : IF g_sim = TRUE GENERATE
     jesd204b_avs_clk <= rxlink_clk;
   END GENERATE;
 
+  -- For synthesis the avs clock is driven by the mm_clk as usual
   gen_synthclock : IF g_sim = FALSE GENERATE
     jesd204b_avs_clk <= mm_clk;
   END GENERATE;
@@ -252,7 +261,7 @@ BEGIN
         dev_lane_aligned           => dev_lane_aligned_arr(i),           
         dev_sync_n                 => jesd204b_sync_n_arr(i),
         jesd204_rx_avs_chipselect         => '0', --jesd204b_mosi_arr(i).chipselect,
-        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(7 downto 0),
+        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w downto 0),
         jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
         jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
         jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,
@@ -267,7 +276,7 @@ BEGIN
         jesd204_rx_dlb_kchar_data  => (others => '0'), -- debug/loopback testing
         jesd204_rx_frame_error     => '0',             -- jesd204_rx_frame_error.export
         jesd204_rx_int             => OPEN,            -- Connected to status IO in example design 
-        jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
+        jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*c_jesd204b_rx_data_w+c_jesd204b_rx_data_w-1 DOWNTO i*c_jesd204b_rx_data_w),
         jesd204_rx_link_valid             => jesd204b_rx_link_valid_arr(i),
         jesd204_rx_link_ready             => '1',
         pll_ref_clk                => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) 
@@ -280,7 +289,7 @@ BEGIN
         rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),    -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
         rxphy_clk                  => OPEN,                   -- Not used in Subclass 0 (Intel JESD204B-UG p63)
         sof                        => OPEN,
-        somf                       => jesd204b_rx_somf_arr(4*i+3 downto 4*i),
+        somf                       => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
         sysref                     => jesd204b_sysref_2
       );
 
@@ -328,21 +337,21 @@ BEGIN
       BEGIN
         IF rising_edge(rxframe_clk) THEN
           IF rxframe_rst_n_arr(i) = '0' THEN
-            rx_src_out_arr(i).data(15 downto 0)  <= (OTHERS => '0');
-            rx_src_out_arr(i).channel(1 downto 0)  <= (OTHERS => '0');
+            rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)  <= (OTHERS => '0');
+            rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= (OTHERS => '0');
             f2_div1_cnt_arr(i) <= '0';
           ELSE
             rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
             IF jesd204b_rx_link_valid_arr(i) = '0' THEN
-              rx_src_out_arr(i).data(15 downto 0)  <= (OTHERS => '0');
-              rx_src_out_arr(i).channel(1 downto 0)  <= (OTHERS => '0');
+              rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)  <= (OTHERS => '0');
+              rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= (OTHERS => '0');
             ELSE
               IF f2_div1_cnt_arr(i) = '1' THEN
-                rx_src_out_arr(i).data(15 downto 0)    <= jesd204b_rx_link_data_arr(32*i+15 downto 32*i);
-                rx_src_out_arr(i).channel(1 downto 0)  <= jesd204b_rx_somf_arr(4*i+1 downto 4*i);
+                rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)    <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w*i+c_jesd204b_rx_framer_data_w-1 downto c_jesd204b_rx_data_w*i);
+                rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_framer_somf_w-1 downto c_jesd204b_rx_somf_w*i);
               ELSE
-                rx_src_out_arr(i).data(15 downto 0)    <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16);
-                rx_src_out_arr(i).channel(1 downto 0)  <= jesd204b_rx_somf_arr(4*i+3 downto 4*i+2);
+                rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w-1 downto 0)    <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w*i+c_jesd204b_rx_data_w-1 downto c_jesd204b_rx_data_w*i+c_jesd204b_rx_framer_data_w);
+                rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w-1 downto 0)  <= jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i+c_jesd204b_rx_framer_somf_w);
               END IF; 
               f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
             END IF; 
@@ -413,7 +422,7 @@ BEGIN
   u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
     g_nof_mosi    => g_nof_channels,
-    g_mult_addr_w => 8 
+    g_mult_addr_w => c_jesd204b_mm_addr_w 
   )
   PORT MAP (
     mosi     => jesd204b_mosi,

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd

@@ -37,7 +37,6 @@ USE dp_lib.dp_stream_pkg.ALL;
 ENTITY ip_arria10_e2sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );

libraries/technology/jesd204b/tech_jesd204b.vhd

@@ -56,7 +56,6 @@ USE work.tech_jesd204b_component_pkg.ALL;
 ENTITY tech_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_technology          : NATURAL := c_tech_arria10_e1sg;
     g_nof_channels        : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
@@ -92,7 +91,6 @@ BEGIN
     u0 : ENTITY work.tech_jesd204b_arria10_e1sg
     GENERIC MAP(
       g_sim                => g_sim,                
-      g_sim_level          => g_sim_level,          
       g_nof_channels       => g_nof_channels,      
       g_direction          => g_direction
     )
@@ -121,7 +119,6 @@ BEGIN
     u0 : ENTITY work.tech_jesd204b_arria10_e2sg
     GENERIC MAP(
       g_sim                => g_sim,                
-      g_sim_level          => g_sim_level,          
       g_nof_channels       => g_nof_channels,      
       g_direction          => g_direction
     )

libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd

@@ -38,7 +38,6 @@ USE work.tech_jesd204b_component_pkg.ALL;
 ENTITY tech_jesd204b_arria10_e1sg IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
@@ -72,7 +71,6 @@ BEGIN
   u_ip_arria10_e1sg_jesd204b : ip_arria10_e1sg_jesd204b
   GENERIC MAP(
     g_sim                => g_sim,                
-    g_sim_level          => g_sim_level,          
     g_nof_channels       => g_nof_channels,      
     g_direction          => g_direction
   )

libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd

@@ -38,7 +38,6 @@ USE work.tech_jesd204b_component_pkg.ALL;
 ENTITY tech_jesd204b_arria10_e2sg IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
@@ -72,7 +71,6 @@ BEGIN
   u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
   GENERIC MAP(
     g_sim                => g_sim,                
-    g_sim_level          => g_sim_level,          
     g_nof_channels       => g_nof_channels,      
     g_direction          => g_direction
   )

libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd

@@ -38,7 +38,6 @@ PACKAGE tech_jesd204b_component_pkg IS
   COMPONENT ip_arria10_e1sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
@@ -72,7 +71,6 @@ PACKAGE tech_jesd204b_component_pkg IS
   COMPONENT ip_arria10_e2sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_sim_level           : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_nof_channels        : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );