Add missing wire out_sosi_arr <= st_sosi_arr.

applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd

@@ -123,6 +123,8 @@ architecture str of sdp_adc_input_and_timing is
   signal nxt_mux_sosi_arr           : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
   signal st_sosi_arr                : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
 begin
+  out_sosi_arr <= st_sosi_arr;
+
   gen_rx : if g_no_rx = false generate
      -----------------------------------------------------------------------------
     -- Time delay: dp_shiftram