From 5f4e824b72347718ff8ca7aa27a57d8d116bb8b4 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 8 Feb 2024 15:54:06 +0100
Subject: [PATCH] Add missing wire out_sosi_arr <= st_sosi_arr.
---
.../lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd | 2 ++
1 file changed, 2 insertions(+)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
index bc44dc392c..82c3b62464 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
@@ -123,6 +123,8 @@ architecture str of sdp_adc_input_and_timing is
signal nxt_mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
signal st_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
begin
+ out_sosi_arr <= st_sosi_arr;
+
gen_rx : if g_no_rx = false generate
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
--
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